Hybrid Memory Clock Synchronization Engine
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Solution Overview
Problem
Legacy hybrid memory module architectures face limitations in implementing a DRAM data clock with selectable frequencies that is synchronized with data written to DRAM during data restore operations, due to timing uncertainties and fixed clock frequency ratios, which affect performance and reliability.
Innovation Solution
A clock synchronization engine at the command buffer generates a synchronized data clock with a phase relationship that compensates for synchronous and asynchronous delays, allowing for selectable frequencies by dividing the local clock signal and using programmable delay elements to ensure accurate data latching during restore operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed divide-by-four relationship is used between the local clock and data clock, then the device complexity is reduced, but the productivity and adaptability are limited due to fixed clock frequency ratios
Solution Approach 1:
The patent implements a dynamic clock frequency selection mechanism that allows the data clock frequency to be adjusted based on operational requirements. Instead of a fixed divide-by-four relationship, the system can dynamically select from multiple division ratios (e.g., divide-by-2, divide-by-4, divide-by-8) to optimize restore operation speed while maintaining manageable device complexity through standardized control logic.
Solution Approach 2:
The system changes the clock frequency parameter by allowing selective division ratios between the local clock and data clock. This enables the data clock frequency to be adjusted according to different operational modes, improving productivity during restore operations without significantly increasing device complexity through the use of multiplexers and control registers.
2Productivity
If the local clock frequency is increased to improve data clock frequency and reduce restore latency, then the productivity is improved, but the use of energy increases due to overclocking
Solution Approach 1:
Instead of increasing the local clock frequency (overclocking), the patent changes the clock division ratio parameter to achieve higher data clock frequencies. This allows the system to maintain the local clock at its rated frequency (avoiding excessive power consumption) while still achieving faster restore latencies by using lower division ratios (e.g., divide-by-2 instead of divide-by-4).
Solution Approach 2:
The system dynamically adjusts the clock division ratio based on operational requirements, allowing flexible optimization of restore latency without permanently overclocking the local clock. This dynamic parameter adjustment enables low-power operation during normal modes while providing high-performance mode when needed, avoiding continuous excessive power consumption.
3Device complexity
If asynchronous delays and synchronous delays are present in the NVDIMM, then the device complexity is reduced by using legacy interfaces, but the measurement precision of timing relationships deteriorates
Solution Approach 1:
The patent introduces a clock synchronization engine as an intermediary component that actively manages and compensates for timing uncertainties. This engine monitors and adjusts for both asynchronous delays (propagation, trace delays) and synchronous delays (logic stage, flip-flop delays), maintaining precise phase relationships between the local clock and data clock while working within the existing legacy interface architecture.
Solution Approach 2:
The clock synchronization engine implements feedback mechanisms to continuously monitor timing relationships and adjust clock phases accordingly. This feedback system compensates for delays introduced by the legacy interface architecture, maintaining measurement precision of timing relationships without requiring a complete redesign of the interface architecture.
4Adaptability or versatility
If selectable data clock frequencies are implemented, then the adaptability is improved, but the device complexity increases due to additional clock management logic
Solution Approach 1:
The clock synchronization engine is designed as a universal component that handles multiple clock division ratios and synchronization requirements through a single integrated architecture. This multi-functional design provides selectable data clock frequencies for different operational modes (normal operation, restore operations, burst transfers) while avoiding the need for separate clock management circuits for each function, thus limiting the increase in device complexity.
Data Source
AI summary
Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller. In other embodiments, certain fixed and/or programmable delay elements can be implemented to compensate for various asynchronous delays.