Hybrid Memory Module Command Replication for Faster Backup Restore
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Solution Overview
Problem
Legacy NVDIMM architectures face throughput limitations in DRAM read and write commands during data backup and restore operations, restricted NVC resource access, and limited programmability of DRAM mode register settings, leading to increased latency and power consumption.
Innovation Solution
Implement a hybrid memory module with a command replicator to generate replicated DRAM commands, a proprietary access engine to expand NVC resource access without impacting host controller access, and a mode register controller to enhance programmability during backup and restore operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If legacy NVDIMM architectures use standard NVC communications interface protocols for DRAM read and write commands during data backup and restore operations, then data integrity is maintained, but throughput is limited due to requiring 128 DRAM clock cycles per DRAM command
Solution Approach 1:
The patent segments the command execution process by introducing a command replicator that divides a single DRAM command into multiple replicated commands. This allows parallel execution of commands to different DRAM devices, effectively bypassing the 128-clock-cycle limitation of the standard NVC interface protocol while maintaining data integrity through coordinated execution of replicated commands.
Solution Approach 2:
The patent implements preliminary action by having the command replicator pre-process and replicate commands before they are executed by the DRAM devices. The replicator generates multiple replicated commands in advance, allowing the system to prepare for high-throughput operations without waiting for the sequential command processing that would otherwise be required by the standard protocol.
2Productivity
If NVC resource access is restricted in host control mode to avoid impacting host memory controller access, then host controller performance is maintained, but NVC resource utilization decreases leading to idle NVC cycles
Solution Approach 1:
The patent implements dynamic resource allocation by enabling the NVC to access control setting registers during host control mode when not actively used by the host controller. The system dynamically switches between host-controlled access and NVC-controlled access based on real-time needs, allowing the NVC to prepare settings and configurations during idle periods without interfering with host operations, thus improving overall resource utilization while maintaining host controller reliability.
3Adaptability or versatility
If DRAM mode register settings are limited in NVC control mode to protect host controller settings, then host controller stability is maintained, but NVC programmability and flexibility decrease
Solution Approach 1:
The patent introduces an intermediary mechanism that allows the NVC to access and modify DRAM mode register settings during NVC control mode while maintaining host controller stability. The system acts as a mediator by enabling NVC programming capabilities when needed for backup and restore operations, while automatically preserving and restoring host controller settings afterward, thus providing both adaptability and stability.
4Use of energy by moving object
If standard NVC communications interface protocols are used for data backup and restore operations, then protocol compatibility is maintained, but power consumption increases due to extended operation duration
Solution Approach 1:
By segmenting commands into replicated parallel operations, the system completes backup and restore operations faster, reducing the total duration of high-power states. Although individual replicated commands may consume similar power to standard commands, the overall operation time is significantly reduced, leading to lower total energy consumption.
Solution Approach 2:
The command replicator enables continuous high-speed data transfer during backup and restore operations by keeping the DRAM interface actively engaged with multiple parallel commands rather than idle waiting periods. This continuous useful action maximizes throughput while minimizing the total operation time, thereby reducing overall power consumption despite the intensive parallel processing required.
Data Source
AI summary
Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.