Hybrid Memory Control Lines Reduce I/O Pads

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Solution Overview

Problem

In fluid ejection devices, such as inkjet printheads, the increasing number of signal lines for controlling circuitry and added features like memory devices leads to a significant increase in die size due to the need for numerous signal pads, which occupies valuable space.

Innovation Solution

Implementing a hybrid memory arrangement with a first memory for identification and a second memory for fluid actuation data, where control lines perform dual tasks to reduce the number of input/output pads, allowing for shared control and data lines, and using a common fire line for both fluid actuation and data communication with the second memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory devices and control circuitry are added to fluid ejection devices, then functionality and versatility are improved, but die size increases due to numerous signal pads

Engineering Contradiction:
ImprovefunctionalityVSAvoiddie size
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent implements a hybrid memory arrangement where a first memory stores identification data and a second memory stores fluid actuation data, allowing the same data bus and control lines to serve multiple functions. The control circuitry sequentially accesses different memory types using the same physical infrastructure, eliminating the need for separate dedicated signal paths for each memory type and reducing the overall number of signal pads required.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines multiple memory devices and control circuitry onto a single die, merging previously separate components into an integrated structure. The identification memory and fluid actuation memory share common data lines, address lines, and control signals, consolidating multiple functions into a unified circuit architecture that reduces the number of external connections needed.

Inventive Principle:
Principle #5Merging (Combining)

2Ease of operation

If the number of signal lines is increased to control additional circuitry and memory, then control capability is improved, but the number of input/output pads increases occupying valuable die space

Engineering Contradiction:
Improvecontrol capabilityVSAvoidinput/output pads area
Core Design Contradiction:
Ease of operationVSArea of stationary object

Solution Approach 1:

The control circuitry uses the same data bus and control lines to communicate with both the identification memory and the fluid actuation memory. By implementing a unified interface architecture where single signal lines perform multiple communication functions depending on the selected memory type, the patent reduces the total number of I/O pads while maintaining full control capability over all device functions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent segments the memory system into distinct functional blocks (identification memory and fluid actuation memory) that can be independently accessed through a shared communication interface. This segmentation allows the same physical signal lines to be selectively connected to different memory types through control logic, enabling multiple functions to be controlled through a reduced set of I/O pads.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11999162B2Fluid ejection devices including a first memory and a second memory
Publication Date: 2024.06.04 HEWLETT PACKARD DEVELOPMENT COMPANY LP
  • US11999162B2 patent drawing
  • US11999162B2 patent drawing
  • US11999162B2 patent drawing

AI summary

An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first data lines, a second data line, a first memory element, and a second memory element. The first memory element is enabled in response to first data on the plurality of first data lines. The second memory element is enabled in response to second data on the second data line.