Hybrid Memory Controller for DRAM and Non-Volatile Storage
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Solution Overview
Problem
Dynamic random access memory (DRAM) integrated circuits consume more power than non-volatile memory integrated circuits, particularly during read operations, and require frequent refresh cycles, which increases power consumption in computing systems.
Innovation Solution
Introducing non-volatile memory controllers and modules, such as NOR FLASH EEPROM, into computer systems to supplement or replace DRAM, utilizing a data communication protocol that addresses the asymmetry in read and write access times and eliminating the need for refresh cycles, thereby reducing power consumption and expanding memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM integrated circuits are used for main memory, then fast read and write access is achieved, but power consumption increases due to refresh cycles and read operations
Solution Approach 1:
The patent merges DRAM and non-volatile memory (NVM) into a single memory module, creating a hybrid memory system that combines the fast access speed of DRAM with the low power consumption and non-volatility of NVM. The memory controller intelligently manages data between the two memory types, allowing frequently accessed data to reside in DRAM while less frequently accessed data is stored in NVM, thus achieving both speed and energy efficiency
Solution Approach 2:
The patent changes the volatility parameter of the memory system by introducing non-volatile memory components. This allows the system to maintain data without continuous power supply or refresh cycles, fundamentally altering the power consumption characteristics while maintaining acceptable access speeds through intelligent data placement and caching strategies
2Reliability
If DRAM integrated circuits are used for main memory, then volatile storage is achieved, but refresh cycles are required which increase power consumption
Solution Approach 1:
The patent segments the memory system into volatile DRAM portion and non-volatile memory portion. The DRAM segment provides fast access and holds frequently used data, while the NVM segment provides persistent storage without requiring refresh cycles. This segmentation allows the system to achieve data retention reliability through the NVM portion while eliminating the continuous power consumption associated with DRAM refresh operations
Solution Approach 2:
The non-volatile memory portion serves itself by maintaining data without external refresh operations. Unlike DRAM that requires periodic refresh cycles to maintain data integrity, the NVM inherently retains data without power or refresh, making the system self-sufficient for data preservation and eliminating a major source of power consumption
3Use of energy by moving object
If non-volatile memory is introduced to replace DRAM, then power consumption is reduced, but read and write access times become asymmetric
Solution Approach 1:
The patent acknowledges and utilizes the asymmetric access characteristics of non-volatile memory by implementing a hybrid architecture with DRAM. The system accepts the write-speed limitation of NVM but compensates by using fast DRAM for write operations and leveraging NVM's strength in persistent storage. The memory controller optimizes data placement to minimize the impact of NVM's asymmetric access times on overall system performance
Solution Approach 2:
The DRAM component acts as an intermediary between the processor and non-volatile memory. It buffers write operations to NVM, absorbing the speed mismatch between fast processor writes and slower NVM writes. This intermediary layer masks the asymmetric access times of NVM, providing the processor with fast write performance while still benefiting from NVM's low power consumption and persistence
4Quantity of substance
If non-volatile memory modules are used, then memory capacity is expanded, but device complexity increases due to additional controllers and protocols
Solution Approach 1:
The patent designs the memory module to be universal, compatible with standard memory interfaces and protocols. The hybrid memory module can be addressed and controlled using conventional memory controller commands, allowing it to work with existing system architectures without requiring completely new control mechanisms. This multi-functionality approach expands capacity while minimizing the increase in device complexity
Data Source
AI summary
An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.