Hybrid Memory Controller Segmentation for DRAM and SCM Access
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Solution Overview
Problem
Hybrid memory systems face limitations in high-speed memory access and power consumption due to the use of a single memory channel for data transfer between DRAM and SCM, which restricts access speed and increases power consumption due to stray capacitance in wiring.
Innovation Solution
A multi-channel memory chip with a cross-bar switch and a memory controller that provides separate channels for DRAM and SCM, allowing for independent data transfer and timing training to optimize data access and reduce power consumption by minimizing wiring length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single memory channel is used for data transfer between DRAM and SCM, then device complexity is reduced, but memory access speed deteriorates and power consumption increases
Solution Approach 1:
The memory channel is segmented into multiple independent channels (first memory channel for DRAM, second memory channel for SCM). Each channel operates independently to transfer data between the memory controller and respective memory devices, enabling parallel access and improving overall memory access speed without requiring a completely complex new architecture.
2Use of energy by moving object
If a single memory channel is used for data transfer between DRAM and SCM, then wiring length is reduced, but power consumption increases due to stray capacitance
Solution Approach 1:
The power consumption issue is addressed by segmenting the memory interface into separate channels for DRAM and SCM. Each channel has its own dedicated wiring and control logic, which reduces the overall stray capacitance compared to a single high-speed channel serving both memory types. This segmentation allows for optimized power management while maintaining high access speeds.
3Ease of operation
If the same memory channel is used for both DRAM and SCM, then ease of operation is improved, but access speed to each memory device deteriorates
Solution Approach 1:
The memory controller is divided into separate control units for each memory channel - a first control unit for DRAM operations and a second control unit for SCM operations. Each control unit is optimized for its specific memory type, maintaining ease of operation through specialized control logic while enabling simultaneous high-speed access to both DRAM and SCM devices through parallel channels.
4Productivity
If separate channels are provided for DRAM and SCM, then memory access speed is improved, but device complexity increases
Solution Approach 1:
The memory system is segmented into distinct channels with dedicated control units, cross-bar switches, and timing training mechanisms for each memory type. This segmentation enables parallel data transfer operations between the memory controller and multiple memory devices, significantly improving productivity and data transfer efficiency while managing complexity through modular, specialized components rather than a monolithic complex system.
Data Source
AI summary
Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a memory array including a plurality of memory cells; a memory controller that transmits a command signal, address signals and further provides and receives data signals; a first port including: a first command terminal that receives the first command signal from the memory controller, first address terminals that receive first address signals from the memory controller, and first data terminals that receive first data signals from the memory controller and further transmit first data signals to the memory controller; and a second port including: a second command terminal that receives a second command signal from the memory controller; second address terminals that receive second address signals from the memory controller and second data terminals that receive second data signals from an external apparatus other than the memory controller and further transmit second data signals to the external apparatus.