Hybrid Memory Module With CRC Recovery for DRAM-Flash Data Integrity
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Solution Overview
Problem
Current memory technologies face challenges with volatile DRAM's high cost and data loss upon power removal, and Flash memory's limited random-access capabilities and finite program-erase cycles, making them unsuitable for high-reliability data storage.
Innovation Solution
A hybrid memory module combining volatile DRAM and non-volatile Flash memory subsystems, with a dedicated data path and module controller for efficient data transfer and management, enabling seamless integration and operation as a standard DIMM without BIOS changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile DRAM is used for system memory, then fast random access is achieved, but data is lost upon power removal and cost increases
Solution Approach 1:
The memory module is segmented into two distinct subsystems: a volatile memory subsystem (DRAM) for fast random access and a non-volatile memory subsystem (Flash) for data persistence. This segmentation allows each subsystem to perform its specialized function optimally while working together as an integrated memory system.
Solution Approach 2:
A module controller acts as an intermediary between the volatile and non-volatile memory subsystems, managing data transfers, wear leveling, and coordination. The controller enables seamless operation by handling the complexity of interfacing between different memory types with different access characteristics.
2Quantity of substance
If high density DRAM is used to increase memory capacity, then capacity is improved, but cost increases significantly
Solution Approach 1:
The patent merges Flash memory (high capacity, low cost) with DRAM (fast access) into a hybrid memory module. This combination allows the system to achieve high capacity at lower cost by using Flash for bulk storage while maintaining fast access performance through the DRAM component for active data.
Solution Approach 2:
The invention changes the parameter composition of the memory system by combining two different memory technologies with complementary characteristics. This parameter change enables the system to achieve a better balance between capacity, cost, and performance than using either memory type alone.
3Reliability
If Flash memory is used for storage, then data persistence is achieved, but random access capability is limited
Solution Approach 1:
The memory module is segmented into two distinct subsystems: a volatile memory subsystem (DRAM) for fast random access and a non-volatile memory subsystem (Flash) for data persistence. This segmentation allows each subsystem to perform its specialized function optimally while working together as an integrated memory system.
Solution Approach 2:
The patent adds a temporal dimension to memory operation by using DRAM for immediate/fast access and Flash for persistent/long-term storage. This dimensional approach allows the system to satisfy both speed and persistence requirements by operating in different time scales and access modes.
4Quantity of substance
If Flash memory is used for high capacity storage, then capacity is improved, but program-erase cycles are limited causing wear
Solution Approach 1:
A module controller acts as an intermediary between the volatile and non-volatile memory subsystems, managing data transfers, wear leveling, and coordination. The controller enables seamless operation by handling the complexity of interfacing between different memory types with different access characteristics.
Solution Approach 2:
The module controller implements wear leveling algorithms that monitor and manage the program-erase cycle distribution across Flash memory blocks. This feedback mechanism ensures uniform wear distribution, extending the overall endurance of the Flash memory subsystem while maintaining high capacity.
Data Source
AI summary
A memory module comprises dynamic random access memory (DRAM), Flash memory, and a module controller. The module controller is configured to receive data to be transferred from the DRAM to the Flash memory, compute first cyclic redundancy check (CRC) codes for the data, and write the data into the Flash memory. The module controller is further configured to read the data from the Flash memory, compute second CRC codes for the data read from the Flash memory, and transfer the data to the DRAM. The module controller is further configured to compare the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the Flash memory, read a data segment of the data from the DRAM that include the one or more erroneous data bits, correct the one or more erroneous data bits in the data segment, and write the data segment back into the DRAM.