Hybrid Semiconductor Memory Cell for Fast Operation and Data Retention
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Solution Overview
Problem
Existing semiconductor memory devices either lose data when power is discontinued (volatile memory) or operate slowly (non-volatile memory), lacking a universal type memory that balances speed with data retention.
Innovation Solution
A semiconductor memory array comprising capacitorless transistors with floating bodies and resistance change elements, where data is stored in the capacitorless transistor during power and transferred to the nonvolatile resistance change element upon power loss or backup instruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory devices are used to retain data without power, then data retention capability is improved, but operation speed deteriorates
Solution Approach 1:
The patent combines volatile memory (capacitorless transistor with floating body) and non-volatile memory (resistance change element) into a single hybrid memory cell. The volatile component provides fast read/write operations while the non-volatile component ensures data retention without power, resolving the speed-retention contradiction through functional integration
Solution Approach 2:
The hybrid memory cell performs multiple functions within a single structure: it operates as volatile memory during powered operation for speed, and automatically transitions to non-volatile storage when power is lost for data retention. This multi-functionality eliminates the need to choose between speed and retention
2Reliability
If hybrid memory structure is implemented to provide both volatile and non-volatile functionality, then data retention and speed are improved, but device complexity increases
Solution Approach 1:
The patent merges the volatile transistor and non-volatile resistance element into a tightly integrated hybrid cell structure where components share common elements (such as the floating body serving both as transistor channel and charge storage). This integration reduces overall device complexity compared to separate volatile and non-volatile memory structures
Solution Approach 2:
The resistance change element is embedded within or alongside the transistor structure, with the floating body nested between the resistance element and the transistor gate. This nested arrangement allows both functions to coexist in a compact configuration, minimizing the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables fast operation akin to volatile memories while retaining data when power is off, with the added benefit of compact size comparable to traditional volatile or non-volatile devices.
Implementation Method 1
a nonvolatile memory comprising a resistance change element configured to store the data stored in the capacitorless transistor upon transfer thereto
Data Source
AI summary
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.