Hybrid Memory Module EDC and Wear Leveling
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Solution Overview
Problem
Hybrid volatile/non-volatile memory systems face challenges due to the sensitivity of DRAM to soft errors and the poor endurance of NVM, requiring effective error-detection and correction techniques and wear leveling to maintain performance and longevity.
Innovation Solution
A hybrid memory system that employs a DRAM cache to store data from NVM, using an interface to map and store cached data and error-detection/correction bits, and implements a wear leveling scheme to distribute write operations evenly across NVM, thereby combining the benefits of nonvolatility, error-tolerance, and reduced cost with the speed and durability of DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used to cache data from NVM, then access speed is improved, but DRAM sensitivity to soft errors increases system reliability requirements
Solution Approach 1:
The patent introduces an intermediary error-detection and correction mechanism between DRAM and NVM. EDC bits are calculated for data blocks stored in DRAM cache, and these EDC bits are persisted alongside the data in NVM. When data is read from NVM or accessed in DRAM, the EDC bits enable detection and correction of soft errors, thus mediating the reliability issue while maintaining the speed advantage of DRAM caching.
Solution Approach 2:
The system performs preliminary error-detection and correction by calculating EDC bits before data is written to NVM or when data is loaded into DRAM cache. This preliminary action ensures that error protection is established in advance, allowing the system to maintain high-speed DRAM access while preemptively addressing potential soft errors that may occur during volatile memory operations.
2Duration of action of stationary object
If NVM is used for bulk storage, then nonvolatility and cost-effectiveness are improved, but write endurance deteriorates
Solution Approach 1:
The patent implements a copying strategy where frequently accessed data is copied from NVM to DRAM cache. The original data remains in NVM, and the DRAM cache serves as a volatile copy for rapid access. This reduces write operations to NVM since updates can be performed in the faster DRAM cache first, thereby preserving NVM write endurance while maintaining data persistence.
Solution Approach 2:
The system segments data storage across two memory types: NVM for bulk persistent storage and DRAM for active caching. By dividing the storage function between these two media, the system achieves both nonvolatility from NVM and reduced write wear through intelligent data placement and caching policies.
3Reliability
If EDC bits are stored in NVM alongside cached data, then error detection and correction capability is improved, but storage space requirements increase
Solution Approach 1:
The patent employs parameter changes by using compact EDC bit representations that require minimal additional storage space. Rather than storing full redundancy copies of data, the system calculates efficient error-detection codes (such as parity bits or checksums) that occupy a small fraction of the original data size, thus improving error detection capability while minimizing the increase in storage space requirements.
4Duration of action of stationary object
If wear leveling is implemented to distribute write operations, then NVM service life is improved, but system complexity increases
Solution Approach 1:
The patent implements a self-service wear leveling approach where the caching mechanism itself contributes to distributing write operations. By maintaining a DRAM cache that absorbs frequent updates, the system naturally reduces the frequency and intensity of writes to NVM without requiring complex external wear leveling controllers. The cache management policies inherently perform wear leveling by batching and optimizing write operations to NVM.
Data Source
AI summary
A hybrid volatile/non-volatile memory employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). The memory supports error-detection and correction (EDC) techniques by allocating a fraction of DRAM storage to information calculated for each unit of stored data that can be used to detect and correct errors. An interface between the DRAM cache and NVM executes a wear-leveling scheme that aggregates and distributes NVM data and EDC write operations in a manner that prolongs service life.