Hybrid Memory Block Erase Control for SLC-to-TLC Switching
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Solution Overview
Problem
Transitioning a memory block from a one bit per memory cell (SLC) operating mode to a three bits per memory cell (TLC) operating mode results in over-erased memory cells, compromising programming performance and degrading the memory cells.
Innovation Solution
A method and apparatus for a hybrid block that can operate in both SLC and TLC storage schemes, where data detection is performed before transitioning to TLC, and memory cells are pre-programmed only if in SLC format, thereby preventing over-erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a memory block transitions from SLC operating mode to TLC operating mode without pre-programming, then the erase operation can be performed directly, but this results in over-erased memory cells that compromise programming performance and degrade memory cell reliability
Solution Approach 1:
The patent applies preliminary action by performing a pre-programming operation on memory cells before executing the erase operation when transitioning from SLC to TLC mode. This pre-programming prepares the memory cells by setting their threshold voltages to appropriate levels, preventing over-erasure and subsequent degradation. The pre-programming step is conditionally executed based on detecting the current storage mode, ensuring that cells are properly prepared before the erase process begins, thereby maintaining both productivity and reliability.
2Device complexity
If the memory block uses a uniform erase scheme for both SLC and TLC modes, then the erase process is simple to implement, but this causes over-erasure when transitioning to TLC mode, compromising programming performance
Solution Approach 1:
The patent implements dynamics by making the erase scheme adaptive rather than static. The system dynamically adjusts the erase process based on the detected storage mode (SLC or TLC) by first performing a pre-programming operation when in SLC mode before erasing. This dynamic adjustment ensures that the erase scheme is optimized for the current operating mode, preventing over-erasure in TLC mode while maintaining simplicity through conditional logic that automatically selects the appropriate erase sequence.
3Reliability
If pre-programming is always performed before erasing, then memory cell degradation is prevented, but this adds unnecessary steps when the memory block is already in TLC mode, reducing operational efficiency
Solution Approach 1:
The patent applies feedback by implementing a detection mechanism that determines the current storage mode (SLC or TLC) of the memory block before executing the erase operation. Based on this feedback information, the system conditionally performs pre-programming only when needed (when SLC mode is detected). This feedback-driven approach prevents unnecessary pre-programming steps in TLC mode, maintaining reliability by preventing over-erasure only when required, while optimizing operational efficiency by avoiding redundant operations.
Data Source
AI summary
The memory device is configured to program and erase data in a memory block according to both an SLC storage scheme and a multiple bits per memory cell (e.g., TLC) storage scheme. In operation, control circuitry receives a command to write data to the memory cells of the memory block in the TLC storage scheme and determine if already data stored in the memory block is in the SLC storage scheme or is in the TLC cell storage scheme. In response to a determination that the data contained in the memory block is in the SLC storage scheme, the control circuitry pre-programs the memory cells of the memory block and then erases the memory cells. In response to a determination that the data contained in the memory block is in the TLC storage scheme, then the control circuitry erases the memory cells without pre-programming.