Hybrid Memory Fine-Grain Remapping for Predictable Performance

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Solution Overview

Problem

The gap in performance predictability between applications that fit in main memory and those that do not, due to software overheads and latency in fetching data from secondary storage, is exacerbated by the high cost and recovery time of terabyte-scale volatile memory, while non-volatile memory offers lower performance and write endurance limitations.

Innovation Solution

A hybrid main memory system combining volatile DRAM with non-volatile memory technologies, utilizing a memory controller for fine-grain remapping and prefetching to maintain performance similar to volatile memory, reducing recovery time and memory errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If terabyte-scale volatile memory is used to maintain large application state, then performance and predictability improve, but cost and recovery time increase significantly

Engineering Contradiction:
Improveperformance predictabilityVSAvoidrecovery time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory system is segmented into two distinct portions: a first portion providing volatile memory with fast access speeds and a second portion providing non-volatile memory with higher capacity and lower cost. This segmentation allows the system to maintain performance for frequently accessed data while using cheaper, higher-capacity storage for less critical data, resolving the contradiction between performance and recovery time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different quality characteristics are assigned to different memory portions: the first portion has high speed but high cost and limited capacity, while the second portion has lower speed but lower cost and higher capacity. The memory controller selectively accesses appropriate portions based on data importance and access patterns, achieving local optimization that balances performance and recovery time.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If non-volatile memory is used to reduce cost and capacity, then storage capacity increases, but performance and write endurance decrease

Engineering Contradiction:
Improvememory capacityVSAvoidaccess speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The memory system divides storage into two segments with different characteristics: volatile memory for high-speed access and non-volatile memory for high-capacity, low-cost storage. This segmentation allows the system to achieve high overall capacity while maintaining fast access speeds for critical data through selective placement and access strategies.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory controller acts as an intermediary between the processor and the two memory portions. It manages data transfer between volatile and non-volatile memory, caches frequently accessed data in the fast volatile portion, and provides a unified memory interface to the processor, thereby maintaining high performance while utilizing the high capacity of non-volatile memory.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If fine-grain remapping is used to maintain performance, then latency and overhead are reduced, but system complexity increases

Engineering Contradiction:
ImprovelatencyVSAvoidremapping complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The memory controller autonomously performs fine-grain remapping operations without requiring software intervention. It automatically manages data transfer between memory portions, updates translation lines, and maintains performance characteristics, thereby reducing latency and overhead while containing complexity within the hardware controller rather than the software system.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system performs preliminary actions by pre-translating address spaces and pre-positioning data in the volatile memory portion before it is needed. Translation lines are maintained in advance to map virtual addresses to physical locations in either memory portion, enabling fast access without runtime remapping overhead and reducing overall system complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9898410B2Hybrid main memory using a fine-grain level of remapping
Publication Date: 2018.02.20 INTEL CORP
  • US9898410B2 patent drawing
  • US9898410B2 patent drawing
  • US9898410B2 patent drawing

AI summary

Accessing a hybrid memory using a translation line is disclosed. The hybrid memory comprises a first portion. The translation line maps a first physical memory address to a first line in the first portion. Said mapping provides an indication that the first line is not immediately accessible in the first portion.