Hybrid Memory Module With DRAM Cache for Flash Wear Reduction

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Solution Overview

Problem

Existing memory systems face challenges in efficiently combining the speed and durability of dynamic random-access memory (DRAM) with the non-volatility and cost-effectiveness of non-volatile memory, while managing disparate access granularities and minimizing wear on non-volatile components.

Innovation Solution

A hybrid memory module that integrates DRAM components to cache a subset of data from non-volatile memory, using an address buffer component with SRAM to manage communication and reduce memory transactions, thereby enhancing read and write access speeds and reducing wear on non-volatile memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If non-volatile memory is used to provide non-volatility and cost-effectiveness, then storage capacity and cost efficiency are improved, but access speed deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidaccess speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The memory system is segmented into two distinct parts: non-volatile memory for bulk storage and DRAM cache for fast access. This segmentation allows each component to perform its specialized function optimally - non-volatile memory provides large capacity at low cost, while DRAM cache provides high-speed access to frequently used data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A DRAM cache component is introduced as an intermediary between the host and non-volatile memory. This intermediary layer stores copies of frequently accessed data, mediating between the host's need for fast access and non-volatile memory's slower but cheaper storage capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If DRAM is used to improve access speed, then read and write performance are improved, but cost efficiency and non-volatility deteriorate

Engineering Contradiction:
Improveaccess speedVSAvoidcost efficiency
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

Instead of making the entire memory system fast and expensive (all DRAM), only a portion - the cache - is made fast using DRAM. The bulk storage remains in non-volatile memory, achieving local optimization where speed is needed while maintaining cost efficiency overall.

Inventive Principle:
Principle #3Local quality

3Device complexity

If direct access to non-volatile memory is performed, then simplicity is maintained, but wear on non-volatile components increases

Engineering Contradiction:
Improvesystem simplicityVSAvoidcomponent durability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The DRAM cache acts as an intermediary that absorbs write operations, protecting the non-volatile memory from excessive wear. Writes are performed in the durable DRAM cache, while non-volatile memory is accessed less frequently, extending its lifespan.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Speed

If DRAM cache is introduced to improve access speed, then read performance is improved, but device complexity increases

Engineering Contradiction:
Improveread performanceVSAvoidmemory architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges DRAM and non-volatile memory into a unified hybrid memory module that presents a single interface to the host. This combining approach consolidates the complexity within the module while maintaining simplicity at the system level.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The hybrid memory module provides multiple functions through a single integrated design: it offers both fast DRAM caching and non-volatile storage, manages its own cache policies, and presents a unified interface to the host, eliminating the need for separate control logic outside the module.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12561244B2Hybrid memory
Publication Date: 2026.02.24 RAMBUS INC
  • US12561244B2 patent drawing
  • US12561244B2 patent drawing
  • US12561244B2 patent drawing

AI summary

A hybrid memory includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static random-access memory (SRAM) cache of addresses for data cached in DRAM.