Hybrid Memory Interface ECC Consolidation
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Solution Overview
Problem
In programmable integrated circuits, the use of non-reconfigurable memory interface tiles requires error detection and correction circuits in each tile, leading to a significant number of wires and routing issues due to the need for all data bits to be present simultaneously for encoding and decoding, consuming valuable routing space.
Innovation Solution
The implementation of a hybrid memory interface circuitry that includes both non-reconfigurable ('hard') and reconfigurable ('soft') logic, with soft memory interface logic containing error correction code (ECC) encoder, decoder, write ECC information generator, read modified write (RMW) information buffer, and RMW data merging circuit, allowing for flexible error correction and reduced routing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction circuits are placed in every memory interface tile, then reliability is improved, but device complexity and routing space consumption increase significantly
Solution Approach 1:
The patent extracts the ECC encoding/decoding functionality from individual tiles and consolidates it into a centralized location. Specifically, only the tile containing the soft memory interface logic implements full ECC circuits, while other tiles rely on this centralized implementation, thereby eliminating redundant ECC circuits across multiple tiles.
Solution Approach 2:
The centralized ECC circuitry in the soft memory interface logic tile serves multiple tiles simultaneously. This universal implementation allows a single set of ECC circuits to perform error detection and correction for data from multiple memory interface tiles, reducing overall system complexity while maintaining reliability.
2Reliability
If all data bits are routed to each tile for simultaneous encoding and decoding, then error correction reliability is improved, but wire quantity and routing space increase significantly
Solution Approach 1:
The patent extracts the requirement for simultaneous data bit availability from distributed tile implementations and consolidates it into a centralized approach. By moving all ECC processing to one location, the system no longer requires all data bits to be routed to every tile, significantly reducing wire quantity.
Solution Approach 2:
The patent merges the ECC encoding and decoding operations into a single centralized location rather than distributing them across multiple tiles. This consolidation allows the system to process error correction for all tiles using a unified approach, eliminating the need for extensive inter-tile data routing required by distributed implementations.
3Productivity
If multiple non-reconfigurable memory interface tiles are used, then memory interface capability is improved, but adaptability and reconfigurability decrease
Solution Approach 1:
The patent introduces dynamic reconfigurability to the memory interface by implementing soft memory interface logic that can be reconfigured. This allows the interface to adapt to different memory configurations and requirements dynamically, combining the high capability of multiple tiles with the flexibility of reconfigurable logic.
Solution Approach 2:
The patent enables parameter changes in the memory interface configuration through reconfigurable soft logic. This allows the interface to change its operational parameters, data width, and error correction characteristics based on specific application requirements, thereby improving adaptability while maintaining high memory interface capability.
Data Source
AI summary
A programmable integrated circuit with memory interface circuitry is provided. The memory interface circuitry may include soft memory interface logic and hard memory interface logic. The soft memory interface logic may be implemented using programmable circuits, whereas the hard memory interface logic may be implemented using non-programmable dedicated circuits. The soft memory interface logic may include error correction code (ECC) encoder and decoder circuits and circuitry for carrying out a read modified write (RMW) operation. The hard memory interface logic may include a write data buffer, a read data buffer, and other circuitry for supporting the RMW operation. The soft memory interface logic is interposed between the hard memory interface logic and the user logic on the programmable integrated circuit.