Hybrid Memory Interface Layout for Higher Bandwidth
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Solution Overview
Problem
Conventional memory systems face challenges in balancing power consumption, latency, bandwidth, and cost, particularly in mobile communication devices, where doubling the number of pins or clock speed to increase bandwidth leads to increased space requirements and electromagnetic interference.
Innovation Solution
A hybrid memory system with 24 data conductors, tailored pin layout, and encoding techniques to enhance bandwidth without doubling pin counts or clock speed, incorporating error correction codes and optimized routing and encoding logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of data conductors is increased from sixteen to twenty-four, then bandwidth is improved, but pin count and routing complexity increase
Solution Approach 1:
The patent segments the 24 data conductors into multiple groups (e.g., first group of 8 conductors, second group of 8 conductors, third group of 8 conductors) that can be independently routed and managed. This segmentation allows the complex 24-conductor interface to be divided into smaller, more manageable units, reducing routing complexity while maintaining the total bandwidth improvement.
2Productivity
If the number of data conductors is increased from sixteen to twenty-four, then bandwidth is improved, but electromagnetic interference increases
Solution Approach 1:
The patent applies different routing strategies to different groups of data conductors based on their specific characteristics and interference patterns. Each group of 8 conductors can be routed through different paths with optimized spacing and shielding, allowing local optimization of electromagnetic interference mitigation while maintaining overall bandwidth improvement from the 24-conductor configuration.
3Productivity
If custom encoding techniques are implemented for the pin layout, then bandwidth efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements encoding techniques selectively for specific groups of data conductors rather than all 24 conductors uniformly. By applying custom encoding to certain groups (e.g., first group of 8 conductors, second group of 8 conductors) while using standard encoding for others, the system achieves bandwidth efficiency improvements in critical paths without unnecessarily increasing complexity across the entire interface.
Data Source
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AI summary
A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.