Hybrid Memory Management Circuit for Key-Value Store Throughput
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Solution Overview
Problem
Integrated circuits face challenges in achieving high throughput, low latency, and low power consumption while supporting various data processing applications, particularly in key-value stores, due to the need for flexible hardware configurations that accommodate different memory types and protocols.
Innovation Solution
A circuit with multiple memory interfaces and a memory management circuit that routes data based on a data transfer criterion, utilizing a hybrid memory architecture combining SSDs and DRAMs to optimize storage density, throughput, and power efficiency, allowing for scalable storage and efficient data distribution across different memory types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional server uses main memory for key-value store with a network adapter, then the implementation is simple and cost-effective, but the throughput is limited and power consumption is high
Solution Approach 1:
The patent segments the key-value store data across multiple memory types (DRAM, SSD, and other non-volatile memories) rather than using a single main memory. The memory management circuit divides data into hot, warm, and cold segments, placing frequently accessed data in DRAM for high-speed access and less frequently accessed data in SSDs or non-volatile memories, thereby achieving high throughput while reducing overall power consumption.
Solution Approach 2:
The system dynamically manages data distribution across different memory types based on access patterns and data transfer criteria. The memory management circuit adapts the routing of data requests in real-time, selecting the most appropriate memory interface (DRAM or SSD) based on current workload characteristics, which optimizes both throughput and power efficiency.
2Productivity
If different types of memory are used to store data in key-value store, then storage density and performance are improved, but the device complexity increases due to multiple memory interfaces and routing requirements
Solution Approach 1:
The memory management circuit is designed as a universal controller that can manage multiple types of memory interfaces (DRAM, SSD, and other non-volatile memories) through a unified architecture. This multi-functional circuit handles routing, data transfer, and memory management tasks across different memory types, reducing the need for separate control logic for each memory interface and thereby managing complexity while supporting diverse memory technologies.
Solution Approach 2:
The memory management circuit acts as an intermediary between the processor and multiple memory types. It abstracts the complexity of different memory interfaces by providing a unified interface to the processor while handling the intricate details of data routing, address translation, and protocol conversion to and from different memory technologies, thus isolating the processor from memory interface complexity.
3Quantity of substance
If data is distributed across DRAM and SSDs, then storage capacity and cost-effectiveness are improved, but access latency increases for data stored in SSDs
Solution Approach 1:
The patent applies local quality by placing data with different access characteristics in different memory locations. Frequently accessed data (hot data) is stored in DRAM with fast access times, while less frequently accessed data (cold data) is stored in SSDs or non-volatile memories. This spatial differentiation of data quality ensures that critical data operations experience low latency while maximizing overall storage capacity.
Solution Approach 2:
The system performs preliminary actions by pre-loading frequently accessed data into DRAM from SSDs or non-volatile memories before actual access requests occur. The memory management circuit anticipates data access patterns and proactively transfers data to faster memory, thereby reducing access latency for subsequent operations while maintaining large storage capacity in slower but higher-capacity media.
Data Source
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AI summary
A circuit for processing data is described. The circuit comprises an input (306) for receiving a request for implementing a key-value store data transaction; a plurality of memory interfaces (314, 318) associated with different memory types enabling access to a plurality of memory devices (316, 320) associated with a key-value store; and a memory management circuit (108, 304) controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion.