Hybrid Memory Module Layout for CPU Bus Throughput

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Solution Overview

Problem

The existing memory systems face a bottleneck in data read throughput due to the significant difference in throughput between DRAMs and SSDs, which limits the computing power of information processing apparatuses like servers handling big data, especially when high-speed DRAMs and lower-speed but larger-capacity flash memories are mounted on the same DIMM.

Innovation Solution

A hybrid memory module is designed with memory controllers placed close to the DIMM socket terminal and high-speed memories on the back surface, while nonvolatile memories are arranged farther away, optimizing the arrangement to maximize CPU memory bus throughput by minimizing wiring lengths and securing bandwidth for low-speed flash memories in an interleaved fashion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If flash memories and DRAMs are mounted on the same DIMM to increase capacity, then storage capacity is improved, but data read throughput deteriorates due to the speed difference between flash memories and DRAMs

Engineering Contradiction:

Improvestorage capacityVSAvoiddata read throughput

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The DIMM is segmented into distinct mounting regions: high-speed DRAMs are mounted on the back surface close to the DIMM socket terminal, while lower-speed flash memories are mounted on the side farther from the terminal. This spatial segmentation allows each memory type to operate in its optimal performance zone, with DRAMs providing high-speed data access and flash memories providing additional capacity without significantly impacting overall throughput

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the DIMM are assigned different quality characteristics based on their distance from the socket terminal. The region close to the terminal (back surface) is optimized for high-speed operations with DRAMs, while the region farther away (side) is optimized for high-capacity storage with flash memories. This local quality differentiation resolves the contradiction by allowing each memory type to fulfill its specific functional role

Inventive Principle:

Principle #3Local quality

2Productivity

If memory components are arranged to maximize DRAM performance by placing them close to the DIMM socket terminal, then CPU memory bus throughput is improved, but mounting space for large-capacity flash memories deteriorates

Engineering Contradiction:

ImproveCPU memory bus throughputVSAvoidmounting space

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The mounting layout transitions from a two-dimensional planar arrangement to a three-dimensional utilization of the DIMM structure. DRAMs are mounted on the back surface (utilizing the Z-dimension), while flash memories are mounted on the side surface (utilizing the X-Y plane). This dimensional transition allows both high-speed performance components and high-capacity storage components to coexist without compromising mounting space for either type

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If low-speed flash memories are mounted close to the DIMM socket terminal to increase capacity, then storage capacity is improved, but CPU memory bus throughput deteriorates due to bandwidth consumption

Engineering Contradiction:

Improvestorage capacityVSAvoidCPU memory bus throughput

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory controller acts as an intermediary between the CPU memory bus and the mixed memory types. It manages data flow by prioritizing high-speed DRAM operations for time-critical data while handling flash memory operations for capacity-critical data, thereby maintaining overall CPU memory bus throughput while accommodating large-capacity storage

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9569144B2DRAM with SDRAM interface, and hybrid flash memory module

Publication Date: 2017.02.14 HITACHI VANTARA LTD

AI summary

When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.