Hybrid Memory Page Table Translation for Data Migration
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Solution Overview
Problem
Combining hybrid memory with physical large page technology is challenging due to reduced memory hit rates and address translation performance when frequently written/read data is migrated from nonvolatile memory to volatile memory, altering the granularity of memory addressing.
Innovation Solution
A memory access method that maintains a large page in the page table while allowing individual small pages within the large page to be migrated to volatile memory, ensuring high TLB hit rates and efficient address translation by updating the page table buffers to track migrated data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a physical large page of NVM is replaced with a plurality of physical small pages to migrate frequently written/read data, then data migration capability is improved, but address translation performance deteriorates
Solution Approach 1:
The patent segments a large page into multiple small pages, allowing selective migration of frequently accessed data to DRAM while maintaining the large page structure in the page table. This enables fine-grained data management without breaking the large page address translation mechanism, thus improving data migration capability while preserving address translation performance.
Solution Approach 2:
The patent implements a nested page structure where small pages are nested within a large page. The large page remains in the page table for address translation, while small pages inside it can be individually managed and migrated. This nested structure allows the system to maintain large page address translation performance while enabling small page-level data migration flexibility.
2Speed
If a frequently written/read storage block in NVM is migrated to DRAM, then memory access speed is improved, but memory system complexity increases
Solution Approach 1:
The patent segments the memory system into a large page structure (for address translation) and small page units (for data migration). This segmentation allows the memory management unit to handle migration at the small page level while maintaining the simpler large page address translation mechanism, thus improving access speed without proportionally increasing system complexity.
Solution Approach 2:
The patent introduces a memory management unit as an intermediary between the processor and the hybrid memory system. The MMU handles the complex tasks of tracking small page migration status and managing the mapping between large pages and small pages, thereby isolating the complexity from the rest of the system and enabling fast memory access through automated management.
3Measurement precision
If granular memory addressing is changed from physical large page to physical small page, then data migration precision is improved, but TLB hit probability is reduced
Solution Approach 1:
The patent uses a nested structure where small pages are contained within large pages. The page table maintains large page entries for TLB mapping, ensuring high hit probability, while small page boundaries inside the large page enable precise data migration control. This nested approach allows the system to achieve both fine-grained migration precision and coarse-grained address translation efficiency.
Solution Approach 2:
The patent adds a new dimension to the page hierarchy by introducing small pages within large pages. This creates a two-level granularity system where the first level (large pages) maintains TLB hit probability through coarse-grained mapping, and the second level (small pages) provides fine-grained migration precision, effectively resolving the contradiction through dimensional expansion.
Data Source
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Figure 5A
AI summary
Embodiments of this application provide a memory access method and a computer system. The memory access method is applied to a computer system that includes a hybrid memory, and the hybrid memory includes a first memory and a second memory. The method includes: receiving a first access request including a first virtual address; translating the first virtual address into a first physical address according to a first page table buffer in the computer system, where the first physical address is a physical address of a first large page in the first memory, and the first large page includes a plurality of small pages; and when it is determined that data of a first small page in the first large page is migrated to the second memory, accessing the second memory according to a second physical address stored in the first small page, where the second physical address is a physical address of a second small page in the second memory, the second small page stores the data migrated from the first small page, and the second memory includes a plurality of small pages.