Hybrid Memory Pin Layout and Encoding for Higher Bandwidth
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Solution Overview
Problem
Conventional memory systems face challenges in balancing power consumption, latency, bandwidth, and cost, particularly in mobile communication devices, where doubling pin counts or clock speeds to increase bandwidth leads to increased complexity and cost without addressing electromagnetic compatibility issues.
Innovation Solution
A hybrid memory system with 24 data conductors, tailored pin layout, and encoding techniques to enhance bandwidth without doubling pin counts or clock speeds, incorporating error correction codes and optimized routing and encoding logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pin count is doubled to increase bandwidth, then bandwidth is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges command and address signals with data signals by multiplexing them onto the same physical conductors. This allows the system to achieve higher bandwidth without proportionally increasing the pin count, as multiple signal types share the same physical infrastructure. The routing and encoding logic integrates multiple functions into a unified signal transmission path.
Solution Approach 2:
The patent implements dynamic signal routing where conductors can be configured to carry different types of signals (command, address, or data) depending on the operational mode. The system dynamically switches between different signal transmission patterns to optimize bandwidth while managing pin usage efficiently.
2Productivity
If clock speed is doubled to increase bandwidth, then bandwidth is improved, but electromagnetic compatibility issues worsen
Solution Approach 1:
The patent segments the signal transmission into multiple sub-channels and time slots, distributing the data transmission load across multiple conductors and time periods. This segmentation allows for lower individual signal frequencies and reduced electromagnetic interference while maintaining overall bandwidth performance.
Solution Approach 2:
The patent introduces routing and encoding logic as an intermediary layer between the data source and the physical conductors. This intermediary processes and distributes signals in a controlled manner, reducing electromagnetic interference by optimizing signal timing and distribution patterns.
3Productivity
If data conductor count is increased to improve bandwidth, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent makes the data conductors universal by enabling them to carry multiple types of signals (data, command, address) through multiplexing. This multi-functionality reduces the total number of dedicated conductors needed, thereby reducing power consumption while maintaining high bandwidth performance through efficient signal reuse.
Solution Approach 2:
The patent employs periodic signal transmission patterns where conductors are activated in alternating time slots. This periodic action allows for more efficient power management by activating only the necessary conductors at any given time, reducing overall power consumption while maintaining high bandwidth through time-division multiplexing.
Data Source
AI summary
A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.