Hybrid Memory Architecture for PRAM Speed Bottlenecks
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Solution Overview
Problem
Phase change random access memory (PRAM) devices are limited by slower operational speeds compared to dynamic random access memory (DRAM) devices, making them less suitable for high-speed operations due to the need for longer electrical pulses to change the phase of the phase change material for data storage.
Innovation Solution
A non-volatile semiconductor memory apparatus is designed with a first memory area using PRAM cells and a second memory area using floating body cells, where the host interface controls both areas, allowing the second memory area to operate at a faster write speed and providing a temporary storage solution to enhance overall operational speed by using the same address and command signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PRAM cells are used for non-volatile memory storage, then data retention capability is improved, but write speed deteriorates
Solution Approach 1:
The memory apparatus is divided into two distinct memory areas: a first memory area using PRAM cells for non-volatile storage and a second memory area using volatile memory cells for high-speed operations. This segmentation allows each area to optimize for its specific function, resolving the contradiction between data retention and write speed by providing both capabilities in different segments of the same system.
2Reliability
If longer electrical pulses are supplied to change phase change material state, then data storage reliability is improved, but operational speed deteriorates
Solution Approach 1:
The volatile memory area acts as an intermediary between the host interface and the non-volatile PRAM area. When write commands are received, the volatile memory area handles high-speed data acceptance and can immediately service read requests, while the PRAM area performs its slower phase change operations in the background. This intermediary structure allows the system to maintain high operational speed while ensuring reliable data storage in the non-volatile area.
3Speed
If dual memory areas are implemented with different write speeds, then overall operational speed is improved, but device complexity increases
Solution Approach 1:
Both memory areas share common control interfaces including the host interface, address bus, and command bus. This universal interface design allows a single control logic structure to manage both the PRAM area and the volatile memory area, reducing the increase in device complexity that would otherwise result from having separate control circuits for each memory type.
Data Source
AI summary
A non-volatile semiconductor memory apparatus includes a first memory area configured to include a plurality of non-volatile memory cells, a second memory area configured to include a plurality of memory cells whose write speed is faster than the plurality of non-volatile memory cells, and a host interface configured to control the first and second memory areas, wherein the first and second memory areas are configured to be provided with the same address signal and command signal from the host interface.