Hybrid Memory Array Reference Current for Sense Margin Stability

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Solution Overview

Problem

Existing memory arrays using single-ended bit cells suffer from reduced sense margins and shorter lifetimes due to varying current levels over multiple cycles, leading to bit errors and limited storage density, while differential bit cells have improved sense margins but lower storage density.

Innovation Solution

A memory array design that combines single-ended bit cells with differential bit cells, where the reference current is generated by combining a fixed reference current with the sensed currents of differential bit cells, ensuring both types of cells wear at the same rate, thereby maintaining accurate sense margins and increasing storage density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If single-ended bit cells are used, then storage density is increased, but sense margin deteriorates and lifetime is reduced

Engineering Contradiction:

Improvestorage densityVSAvoidsense margin

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent merges single-ended bit cells and differential bit cells into a hybrid memory array. The differential bit cells serve as reference cells that generate reference currents, while the single-ended bit cells store data. This combination allows the system to benefit from both high storage density (from single-ended cells) and improved sense margin (from differential reference cells).

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The differential bit cells act as intermediaries by generating reference currents that are fed back to the sense amplifiers. These reference currents compensate for threshold voltage variations and aging effects, thereby maintaining accurate sensing without requiring the data-storing single-ended cells to have perfect current matching.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If single-ended bit cells are used, then storage density is increased, but lifetime is reduced

Engineering Contradiction:

Improvestorage densityVSAvoidlifetime

Core Design Contradiction:

Quantity of substanceVSDuration of action of stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The differential bit cells provide feedback by generating reference currents that are continuously fed back to the sense amplifiers. This feedback mechanism compensates for threshold voltage variations and aging effects in real-time, extending the operational lifetime of the memory array by maintaining accurate sensing throughout the device's life.

Inventive Principle:

Principle #23Feedback

3Reliability

If differential bit cells are used, then sense margin is improved, but storage density is reduced

Engineering Contradiction:

Improvesense marginVSAvoidstorage density

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

4Device complexity

If reference current is generated using fixed current source, then circuit complexity is reduced, but manufacturing precision deteriorates due to process variations

Engineering Contradiction:

Improvecircuit complexityVSAvoidcurrent matching accuracy

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The differential bit cells serve themselves by generating reference currents based on their own operational characteristics. The reference currents are derived from the actual current levels of the differential reference cells, which automatically adapt to process variations and aging effects. This self-service approach eliminates the need for external fixed current sources with tight manufacturing tolerances.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent changes the parameter used for reference current generation from a fixed value to a dynamically adjusted value based on the actual current levels of the differential reference cells. This parameter change allows the reference current to automatically compensate for process variations and aging effects, improving current matching accuracy without increasing circuit complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20260038605A1Memory array and reference current circuit

Publication Date: 2026.02.05 TEXAS INSTRUMENTS INC

AI summary

A circuit includes a memory array including memory bit cells arranged in rows and columns. A row includes differential reference bit cells and single-ended bit cells, and the reference bit cells include a first set configured to store a first binary value and a second set configured to store a second binary value different from the first binary value. The circuit also includes a control module configured to generate a first reference current and to select the given row for a read operation. The circuit additionally includes an input/output module configured to compare a sensed current of a respective single-ended bit cell of the single-ended bit cells for the read operation to a second reference current. The second reference current is based on the first reference current and respective currents of the first set of reference bit cells and the second set of reference bit cells.