Hybrid Memory Simulator Virtual Address Allocation
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Solution Overview
Problem
Existing simulators for enterprise-scale systems lack the ability to direct memory allocation on hybrid memory systems, as they operate on physical addressing, making it challenging for applications to choose between dynamic random access memory (DRAM) and non-volatile memory (NVM) for data storage, leading to inefficiencies in energy consumption and performance.
Innovation Solution
Implementing a system call that configures virtual address ranges for memory controllers, allowing applications to dictate memory allocation between DRAM and NVM based on OS virtual addresses, thereby redirecting read and writeback traffic to the appropriate memory type, and extending cache block metadata to store virtual addresses for accurate routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored in DRAM for fast access, then speed is improved, but energy consumption increases due to continuous leakage and refresh power
Solution Approach 1:
The memory system is segmented into multiple memory types (DRAM and NVM) with different characteristics. The system divides the address space into regions that map to different memory types, allowing data to be stored in the most appropriate memory type for its access patterns. Frequently accessed data resides in DRAM for speed, while less frequently accessed data is stored in NVM to reduce energy consumption.
Solution Approach 2:
Different regions of the address space are assigned different memory types based on local access patterns. The system provides customized memory characteristics to different data regions - high-speed DRAM for hot data and energy-efficient NVM for cold data - rather than using a uniform memory type throughout the entire system.
2Use of energy by moving object
If data is stored in NVM for energy efficiency, then energy consumption is reduced, but access latency increases
Solution Approach 1:
The system performs preliminary actions by pre-loading data from NVM into DRAM cache before it is actually needed. The cache coherence protocol and virtual address translation mechanisms proactively manage data movement between memory types, ensuring that when data is accessed from NVM, it is first transferred to DRAM to minimize the latency impact on application performance.
3Device complexity
If existing simulators use physical addressing, then device complexity is reduced, but adaptability decreases as applications cannot choose between DRAM and NVM
Solution Approach 1:
The system introduces an intermediary layer (virtual address translation mechanism) between the application and the physical memory system. This intermediary translates virtual addresses to physical addresses while simultaneously determining the appropriate memory type (DRAM or NVM) for data storage. This approach maintains the simplicity of physical addressing in the simulator while adding the adaptability needed for applications to influence memory allocation decisions.
Data Source
AI summary
Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for performing actions during simulation of an application interacting with a hybrid memory system, actions including providing a first range of virtual addresses corresponding to a first type of memory in the hybrid memory system, and a second range of virtual addresses corresponding to a second type of memory in the hybrid memory system, receiving a data packet that is to be stored in the hybrid memory system, determining a virtual address assigned to the data packet, the virtual address being provided in cache block metadata associated with the data packet, and storing the data packet in one of the first type of memory and the second type of memory in the hybrid memory system based on the virtual address, the first range of virtual addresses, and the second range of virtual addresses.