Hybrid Memory Buffer With Stacked Tiles for Bandwidth and Power
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Solution Overview
Problem
Current memory technologies face challenges in optimizing memory bandwidth, power efficiency, and form factor, with DRAM prioritizing capacity and cost at the expense of bandwidth and efficiency, while logic process technology prioritizes power efficiency and bandwidth but at the cost of higher cost and lower memory density.
Innovation Solution
The implementation of hybrid memory systems that combine multiple memory tiles stacked vertically with a hybrid memory buffer, utilizing through-silicon vias for power and data delivery, and employing adaptive power and refresh logic to optimize power usage and error handling, along with scan chain logic for independent addressing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM process technology is used to provide capacity and cost efficiency, then memory capacity and cost are optimized, but memory bandwidth and power efficiency deteriorate
Solution Approach 1:
The patent combines DRAM technology and logic process technology into a hybrid memory system. The logic process technology portion provides high bandwidth and power efficiency, while the DRAM portion provides high capacity and cost efficiency. These two different memory technologies are merged into a single system that can operate together to provide both high capacity and high bandwidth simultaneously, resolving the contradiction between capacity optimization and bandwidth optimization.
Solution Approach 2:
The hybrid memory system is segmented into distinct portions: a logic process technology portion and a DRAM portion. Each segment serves different functions - the logic portion handles bandwidth-critical operations with high power efficiency, while the DRAM portion handles capacity-critical operations with cost efficiency. This segmentation allows the system to optimize different aspects of memory performance separately rather than forcing a single technology to excel at everything.
2Quantity of substance
If DRAM process technology is used to provide capacity and cost efficiency, then memory capacity and cost are optimized, but power efficiency deteriorates
Solution Approach 1:
The patent merges DRAM and logic process technologies in a hybrid memory system where the logic process technology portion provides high power efficiency for bandwidth-critical operations, while the DRAM portion provides high capacity for cost-effective storage. By combining these two technologies, the system achieves both high capacity and high power efficiency simultaneously, resolving the contradiction between capacity optimization and power efficiency optimization.
3Productivity
If logic process technology is used to optimize power efficiency and bandwidth, then power efficiency and bandwidth are improved, but cost and memory density deteriorate
Solution Approach 1:
The patent combines logic process technology and DRAM technology into a hybrid memory system. The logic process technology portion delivers high bandwidth and power efficiency, while the DRAM portion delivers high density and cost efficiency. This merging allows the system to achieve high bandwidth without sacrificing memory density, as each technology contributes its strengths to the overall system performance.
4Use of energy by moving object
If logic process technology is used to optimize power efficiency and bandwidth, then power efficiency and bandwidth are improved, but cost deteriorates
Solution Approach 1:
The patent merges logic process technology and DRAM technology in a hybrid memory system. The logic process technology portion provides high power efficiency for bandwidth-critical operations, while the DRAM portion provides cost-effective high-capacity storage. By combining these technologies, the system achieves high power efficiency without the prohibitive cost of using logic process technology for the entire memory system, as DRAM handles the capacity-critical, cost-sensitive portion.
Data Source
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Figure 3A~3B
AI summary
Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.