Hybrid MEMS ASIC Wafer Stacking for Miniaturization
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Solution Overview
Problem
The existing methods for manufacturing hybrid integrated components with MEMS and ASIC elements face challenges in achieving higher miniaturization while maintaining robustness and reducing production costs, particularly in consumer electronics where space on circuit boards is limited.
Innovation Solution
The method involves creating two independent MEMS/ASIC wafer stacks by processing ASIC substrates, mounting semiconductor substrates, forming micromechanical structures, and then stacking them, with the MEMS elements sandwiched between ASIC elements to create a compact, hermetically sealed component with integrated signal processing and evaluation circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional hybrid integration methods are used with separate ASIC and MEMS substrates, then manufacturing robustness is maintained, but miniaturization is limited and mounting area increases
Solution Approach 1:
The patent merges the ASIC substrate and MEMS substrate into a single integrated substrate structure. The MEMS element is formed directly on the ASIC substrate, eliminating the need for separate substrates and reducing the overall component size while maintaining manufacturing robustness through a unified structure.
Solution Approach 2:
The patent transitions from lateral integration to vertical integration by stacking functional layers in the vertical dimension. The MEMS structure is built vertically on top of the ASIC circuit layer, allowing both functions to coexist in a compact three-dimensional arrangement that reduces the mounting footprint.
2Area of stationary object
If more functions are integrated into smaller terminal equipment, then space efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary structuring of the MEMS element during the ASIC substrate fabrication process itself. The sacrificial layer is deposited and patterned on the ASIC substrate before final ASIC processing, allowing MEMS structure preparation to occur in advance alongside circuit fabrication, thereby simplifying subsequent assembly steps.
Solution Approach 2:
The ASIC substrate serves multiple functions simultaneously: it acts as the base substrate for ASIC circuit fabrication, provides the structural foundation for MEMS element formation, and serves as the final encapsulation layer. This multi-functionality reduces the number of separate components and simplifies the overall manufacturing process.
3Reliability
If vertical hybrid integration is implemented with cap wafer, then hermetic sealing is achieved, but manufacturing steps and mounting area increase
Solution Approach 1:
The patent extracts and eliminates the separate cap wafer component from the traditional vertical hybrid integration structure. Instead of adding a cap wafer for hermetic sealing, the ASIC substrate itself is used as the encapsulation layer that provides both structural support and hermetic sealing, thereby reducing manufacturing steps and improving productivity.
Solution Approach 2:
The ASIC substrate performs dual functions as both the circuit carrier and the hermetic encapsulation layer. By using the same substrate for both ASIC mounting and MEMS encapsulation, the patent eliminates the need for separate cap wafers and reduces the number of bonding and sealing steps required in traditional approaches.
Data Source
AI summary
A manufacturing method for hybrid integrated components having a very high degree of miniaturization is provided, which hybrid integrated components each have at least two MEMS elements each having at least one assigned ASIC element. Two MEMS/ASIC wafer stacks are initially created independently of one another in that two ASIC substrates are processed independently of one another; a semiconductor substrate is mounted on the processed surface of each of the two ASIC substrates, and a micromechanical structure is subsequently created in each of the two semiconductor substrates. The two MEMS/ASIC wafer stacks are mounted on top of each other, MEMS on MEMS. Only subsequently are the components separated.