Hybrid Mesh Simulation for 3D Cylindrical Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor device simulators face inefficiencies when simulating 3D cylindrical devices with partially broken rotational symmetry, as they require complex 3D device structure files, which are time-consuming and inefficient, especially for structures like vertical NAND devices with multi-stack processes.
Innovation Solution
A simulation system that divides the semiconductor device into sub-devices based on rotational symmetry, using cylindrical device structure files for symmetric parts and 3D device structure files for asymmetric parts, extracting connection relationships, and applying interface conditions to simulate the device efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a 3D device structure file is used to simulate a cylindrical semiconductor device with partially broken rotational symmetry, then the simulation can handle asymmetric structures, but the simulation time increases significantly and computational efficiency deteriorates
Solution Approach 1:
The patent divides the cylindrical semiconductor device into multiple sub-devices based on rotational symmetry. Each sub-device can be simulated using efficient cylindrical device structure files, while the overall asymmetric structure is captured by combining these segmented parts with appropriate interface conditions. This segmentation allows the system to maintain computational efficiency while handling asymmetric structures.
Solution Approach 2:
The patent applies different device structure file types to different regions of the semiconductor device. Cylindrical device structure files are used for regions with rotational symmetry (sub-devices), while 3D device structure files are used only where necessary to capture local asymmetric features. This local differentiation optimizes computational efficiency without sacrificing the ability to handle asymmetric structures.
2Productivity
If a cylindrical device structure file is used for a 3D cylindrical device with partially broken rotational symmetry, then computational efficiency is maintained, but the simulator cannot accurately represent structures with local deformations
Solution Approach 1:
The patent segments the device into sub-devices that can be represented by cylindrical device structure files, maintaining computational efficiency. The segmentation is designed such that the interface between sub-devices captures the local deformation effects, allowing the overall asymmetric structure to be represented accurately while each sub-device benefits from efficient cylindrical coordinate system simulations.
Solution Approach 2:
The patent introduces interface conditions as intermediaries between sub-devices. These interface conditions act as mediators that transmit the effects of local deformations and asymmetric structures between the cylindrical sub-devices, allowing the system to maintain both computational efficiency and representational accuracy.
3Manufacturing precision
If a 3D device structure file is generated using a figure drawing program, then the device structure can be precisely defined, but the process is time-consuming and complex
Solution Approach 1:
The patent segments the device structure into cylindrical sub-devices that can be defined using efficient cylindrical coordinate systems. This segmentation allows for precise device structure definition while reducing the complexity and time required for structure file generation, as cylindrical coordinates are more efficient to handle than full 3D coordinates.
Solution Approach 2:
The patent transitions from full 3D device structure files to cylindrical device structure files that utilize rotational symmetry. This dimensional change from Cartesian to cylindrical coordinates enables precise representation of cylindrical structures while significantly reducing the computational and temporal complexity of structure file generation.
Data Source
AI summary
Provided is a semiconductor device simulation system and method. The simulation system includes; a device structure file input module configured to receive a plurality of device structure files for a plurality of sub-devices obtained by dividing a semiconductor device to be simulated; a connection relationship extraction module configured to extract connection relationships between the device structure files for the sub-devices; an interface condition application module configured to apply interface conditions to interface points of the device structure files according to the extracted connection relationships; and a simulation module configured to simulate an operation of the semiconductor device using the device structure files for the sub-devices and the interface conditions at interface points of adjacent sub-devices. The simulation system can simulate the semiconductor device using a plurality of device structure files for the sub-devices.