Hybrid Metallization for Void-Free Sub-100nm Interconnects
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in reliably forming sub-100 nm interconnects with low resistance and void-free filling of high-aspect ratio features, as conventional methods lead to high resistance and void formation due to material limitations and selective deposition deficiencies, especially at dimensions below 20 nm.
Innovation Solution
A method involving the deposition of a first barrier layer, followed by filling with a first metal, etching to expose dielectric surfaces, and then depositing a second barrier layer before filling with a second metal, which differs from the first, to reduce resistance and ensure void-free filling of vias and trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional selective deposition methods are used to fill high-aspect ratio features, then deposition coverage is achieved, but voids form due to limited ability to deposit or adhere to sidewalls
Solution Approach 1:
A liner layer is deposited on the sidewalls of the trench before filling the via, creating a preliminary surface that enables subsequent metal deposition. This preliminary action ensures that metal can be properly deposited on the sidewalls, preventing void formation while achieving complete filling.
Solution Approach 2:
The liner layer acts as an intermediary between the dielectric sidewall and the metal fill material. This intermediate layer facilitates proper adhesion and deposition of metal on the sidewall surface, resolving the conflict between achieving coverage and preventing voids.
2Reliability
If a barrier and liner layer is positioned at the via bottom, then adhesion is improved, but via resistance increases due to high resistivities
Solution Approach 1:
The barrier and liner layers are extracted from the via bottom location and repositioned to the trench sidewalls. This removal from the via bottom eliminates the source of high resistance while maintaining adhesion functionality on the sidewalls where it is needed.
Solution Approach 2:
The adhesion function previously provided by barrier/liner layers at the via bottom is copied to the trench sidewalls through the liner layer deposition, maintaining adhesion while eliminating resistance issues.
3Ease of manufacture
If the same metal is used to fill both via and connected trench, then process integration is simplified, but interconnect resistance increases
Solution Approach 1:
Different metal materials are used in different locations: copper is used in the via for low resistance, while cobalt is used in the trench for adhesion and compatibility. This local differentiation optimizes both resistance and process integration by assigning materials based on their specific functional requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces interconnect resistance, eliminates voids, and enhances the reliability and uniformity of semiconductor interconnects, addressing the limitations of conventional methods by maintaining low-k integrity and electrical conductivity.
Implementation Method 1
depositing a first barrier layer upon a top surface of a via and a top surface of a trench
Implementation Method 2
filling the via with a first metal, wherein the first metal completely fills the via and forms a metal layer within the trench
Implementation Method 3
etching the metal layer within the trench to expose dielectric sidewalls of the trench, a top surface of the via, and a dielectric bottom of the trench
Implementation Method 4
depositing a second barrier layer upon the dielectric sidewalls, top surface of the via, and the dielectric bottom of the trench
Implementation Method 5
filling the trench with a second metal different than the first metal
Data Source
AI summary
Methods and apparatus for forming an interconnect, including: depositing a first barrier layer upon a top surface of a via and a top surface of a trench; filling the via with a first metal, wherein the first metal completely fills the via and forms a metal layer within the trench; etching the metal layer within the trench to expose dielectric sidewalls of the trench, a top surface of the via, and a dielectric bottom of the trench; depositing a second barrier layer upon the dielectric sidewalls, top surface of the via, and the dielectric bottom of the trench; and filling the trench with a second metal different than the first metal.