Hybrid Microbump Bonding Structure for Coplanarity and Yield

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Solution Overview

Problem

Existing methods for forming hybrid microbump structures in vertically stacked semiconductor devices face issues of low coplanarity and high costs, leading to poor joint yields due to solder bridging and insufficient flatness.

Innovation Solution

The use of hybrid microbump bonding structures with intermediate redistribution layer (RDL) pads and bump structures having different compositions to improve bonding characteristics and device yields, including copper metal layers with higher solder wettability and nickel or tungsten barrier layers to constrain solder wetting and minimize defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If hybrid microbump structures are formed using existing methods, then integration density is improved, but coplanarity deteriorates and manufacturing costs increase

Engineering Contradiction:

Improveintegration densityVSAvoidcoplanarity

Core Design Contradiction:

Area of moving objectVSManufacturing precision

Solution Approach 1:

The method performs preliminary actions by forming a planarization layer over the microbump structures before bonding, and by pre-aligning the bonding surfaces to ensure coplanarity. This preliminary preparation eliminates the need for post-bonding coplanarity adjustments and prevents solder bridging defects.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

A planarization layer is introduced as an intermediary element between the microbump structures and the bonding interface. This intermediate layer fills in height variations and provides a flat bonding surface, thereby improving coplanarity without requiring modification of the microbump structures themselves.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Area of moving object

If hybrid microbump structures are formed using existing methods, then integration density is improved, but manufacturing costs increase

Engineering Contradiction:

Improveintegration densityVSAvoidmanufacturing costs

Core Design Contradiction:

Area of moving objectVSEase of manufacture

Solution Approach 1:

The method merges the formation of microbump structures with the formation of through-conductor vias into a single integrated process. By combining these two separate manufacturing steps into one, the patent reduces process complexity and manufacturing costs while maintaining the benefits of hybrid microbump structures for improved integration density.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The microbump structures serve a dual function: they provide electrical interconnection and simultaneously act as alignment features for the bonding process. This self-aligning capability eliminates the need for separate alignment procedures and reduces manufacturing complexity.

Inventive Principle:

Principle #25Self-service

3Reliability

If solder material is applied to microbump structures with insufficient flatness, then bonding is achieved, but solder bridging defects increase

Engineering Contradiction:

ImprovebondingVSAvoidsolder bridging defects

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The planarization layer is formed in advance to create a flat bonding surface before solder material is applied. This preliminary action ensures that solder is deposited uniformly across the bonding interface, preventing solder bridging between adjacent microbump structures while maintaining reliable bonding.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances coplanarity and reduces solder bridging defects, resulting in improved joint yields and reduced costs by minimizing solder collapse and bridging during the bonding process.

Implementation Method 1

copper metal layers with higher solder wettability

Methodology Applied

Scientific EffectSolder wettability: Wetting

Implementation Method 2

nickel or tungsten barrier layers to constrain solder wetting and minimize defects

Methodology Applied

Scientific EffectSolder wetting constraint: Wetting

Data Source

PatentUS20250329672A1Bonding scheme to provide improved coplanarity and high joint yields with reduced costs and methods for forming the same

Publication Date: 2025.10.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Vertically stacked semiconductor devices and methods of fabrication thereof include intermediate redistribution layer (RDL) pads underlying a plurality of bump structures. A plurality of intermediate RDL pads may be formed over a first device structure, and at least one bump structure may be formed over each of the intermediate RDL pads. The bump structures include a metal layer and a barrier layer having a lower solder wettability located between the metal layer and the underlying intermediate RDL pad. The barrier layer may constrain solder wetting along the sidewall of the bump structure to minimize solder bridging and other defects. In some embodiments, the intermediate RDL pads may have a relatively lower solder wettability to minimize solder defects. Characteristics of the intermediate RDL pads and the bump structures may be controlled to improve the flatness characteristics of bump structures.