Hybrid Multi-Level Cell Programming Sequences for Write Abort Protection

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Solution Overview

Problem

Existing multiple level cell (MLC) programming techniques face challenges in maintaining data integrity and performance, particularly during write aborts, leading to corruption or ambiguity in lower page data, and incur performance and endurance penalties in prior solutions.

Innovation Solution

A memory device with a controller executing firmware that selects among multiple programming techniques, including a robust technique for data preservation and a high-performance technique, based on criteria such as previous data presence and block status, to determine the optimal programming method for writing data to MLCs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a robust programming technique is used to preserve lower page data during write aborts, then data reliability is improved, but programming speed deteriorates due to two-pass charge configuration programming

Engineering Contradiction:
Improvedata preservation during write abortVSAvoidprogramming speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system dynamically selects between different programming techniques (robust two-pass B-state first technique vs. faster single-pass E-state first technique) based on runtime conditions such as whether lower page data exists and block write status. This dynamic adaptation allows the system to optimize between reliability and speed for each specific programming scenario.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The robust programming technique is applied selectively only to MLCs where lower page data already exists and protection is needed, rather than universally applying it to all MLCs. This localized application preserves data where necessary while maintaining faster programming speeds where possible.

Inventive Principle:
Principle #3Local quality

2Reliability

If reading and saving lower page data in a separate location is performed to protect against corruption, then data reliability is improved, but performance and endurance penalties occur

Engineering Contradiction:
Improvedata protection against corruptionVSAvoidperformance and endurance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary actions by setting appropriate bit conditions in the status register before programming operations. This allows the controller to pre-determine which programming technique should be used based on the state of lower page data, avoiding the need for read-verify-save cycles that penalize performance and endurance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The status register acts as an intermediary that stores bit conditions indicating whether lower page data exists and whether robust programming should be applied. This intermediary mechanism enables the system to make programming decisions without directly reading or copying data, thereby avoiding performance and endurance penalties.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If avoiding upper page write when lower page data already exists is implemented, then data reliability is improved, but performance and endurance penalties occur

Engineering Contradiction:
Improvedata integrityVSAvoidperformance and endurance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system changes the programming parameters by setting specific bit conditions in the status register that indicate whether robust programming should be applied. Based on these parameter changes, the controller selects appropriate programming techniques that maintain data integrity while optimizing performance and endurance, avoiding unnecessary write restrictions.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8634239B2Hybrid multi-level cell programming sequences
Publication Date: 2014.01.21 SANDISK TECHNOLOGIES LLC
  • US8634239B2 patent drawing
  • US8634239B2 patent drawing
  • US8634239B2 patent drawing

AI summary

A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC.