Hybrid Mold Layer Packaging for Compact High-Bandwidth DRAM
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Solution Overview
Problem
Conventional semiconductor packages face challenges in miniaturization due to increased form-factor requirements for stacked DRAM, leading to bulky devices and reliability issues related to solder joint geometry and silicon interposer real-estate.
Innovation Solution
The implementation of hybrid mold layers with different thicknesses and interconnects in semiconductor packages allows for reduced package real-estate, improved signal latency, and enhanced power delivery, facilitating device miniaturization and performance scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor packages use stacked DRAM to increase bandwidth density, then memory bandwidth scaling is improved, but package form-factor expands leading to bulky devices
Solution Approach 1:
The patent transitions from conventional 2D package layouts to a 3D stacked architecture where memory devices are vertically positioned above the processor package substrate. This dimensional change allows multiple memory devices to occupy the same footprint area, increasing bandwidth density without expanding the package form-factor.
Solution Approach 2:
The patent implements a nested structure where memory devices are placed within the vertical space above the processor package substrate, effectively nesting components in three dimensions. The interposer substrate acts as an intermediary layer that enables this nested arrangement, allowing memory devices to be coupled both to the interposer and to each other in a stacked configuration.
2Productivity
If additional DRAM devices are added for performance scaling, then memory capacity increases, but solder joint geometry deteriorates reducing reliability
Solution Approach 1:
The patent moves solder joints from a 2D planar distribution to a 3D vertical arrangement. By stacking memory devices vertically and using an interposer substrate, the solder joints are distributed across multiple height levels rather than competing for the same planar space, maintaining reliable solder joint geometry even as the number of DRAM devices increases.
3Device complexity
If through silicon via interconnects are used for 3D stacking, then vertical integration is improved, but electrical performance deteriorates due to high resistance and signal losses
Solution Approach 1:
The patent employs a composite interconnect structure combining copper or aluminum interconnect lines on the interposer substrate with solder bump interconnects for vertical connections. This composite approach replaces high-resistance through-silicon vias with lower-resistance materials and optimized geometries, maintaining vertical integration while improving electrical performance and reducing signal losses.
Data Source
AI summary
According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.