Hybrid MOSFET Structure for Channel Mobility and Field Control

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Solution Overview

Problem

Existing power MOSFETs face challenges in combining the benefits of planar DMOSFET and trench UMOSFET structures, particularly in achieving high channel mobility and reducing on-resistance while managing electric field crowding at trench corners.

Innovation Solution

A hybrid power MOSFET design incorporating both planar and trench structures with distinct source regions, well regions, and silicide layers, where the trench region is contained within the well regions, and the metal region is in contact with the drift layer, allowing for flexible channel density adjustment and reduced on-resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If trench UMOSFET structure is used, then channel mobility is improved (60-80 cm2/Vs on 11-20 or 10-10 crystal planes), but electric field crowding at trench corners occurs causing reliability issues

Engineering Contradiction:

Improvechannel mobilityVSAvoidelectric field crowding at trench corners

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies local quality by creating different device sections with different characteristics: a first section with planar MOS interface on horizontal surface for high voltage blocking, and a second section with MOS interface on trench sidewall for high channel mobility. Each section is optimized for its specific function, allowing the device to achieve both high speed and reliability.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The device is segmented into multiple sections along the lateral direction: a first section comprising a planar MOS interface for voltage blocking, and a second section comprising a MOS interface on the trench sidewall for current conduction. This segmentation allows each part to perform its optimal function without the drawbacks of the other.

Inventive Principle:

Principle #1Segmentation

2Reliability

If planar DMOSFET structure is used, then electric field distribution is improved, but channel mobility is reduced (15-25 cm2/Vs on 0001 crystal plane)

Engineering Contradiction:

Improveelectric field distributionVSAvoidchannel mobility

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

Inventive Principle:

Principle #1Segmentation

3Area of stationary object

If trench geometry is used, then device area is reduced, but manufacturing complexity increases due to etched non-polar face requirements

Engineering Contradiction:

Improvedevice surface areaVSAvoidmanufacturing process complexity

Core Design Contradiction:

Area of stationary objectVSEase of manufacture

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges the advantages of planar DMOSFET and trench UMOSFET into a hybrid structure that combines both geometries in a single device, allowing the device to achieve both compact area and improved manufacturability.

Inventive Principle:

Principle #5Merging (Combining)

4Adaptability or versatility

If hybrid DMOSFET/UMOSFET structure is used, then flexibility in performance design is improved, but device complexity increases

Engineering Contradiction:

Improveperformance design flexibilityVSAvoiddevice structure complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11862669B2Inversion channel devices on multiple crystal orientations

Publication Date: 2024.01.02 GENESIC SEMICON

AI summary

An embodiment relates to a device comprising a first section and a second section. The first section comprises a first metal oxide semiconductor (MOS) interface comprising a first portion and a second portion. The first portion comprises a first contact with a horizontal surface of a semiconductor substrate and the second portion comprises a second contact with a trench sidewall of a trench region of the semiconductor substrate. The second section comprises one of a second metal oxide semiconductor (MOS) interface and a metal region. The second MOS interface comprises a third contact with the trench sidewall of the trench region. The metal region comprises a fourth contact with a first conductivity type drift layer. The first section and the second section are located contiguously within the device along a lateral direction.