Hybrid MOSFET Output Driver for Gate Oxide Reliability
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Solution Overview
Problem
Existing driving output circuits face challenges in achieving both gate oxide reliability and leakage prevention, especially when power is not supplied, and require a balance between small chip area and low power consumption while being compatible with multiple communication protocols like I2C and I3C.
Innovation Solution
A driving output circuit that includes a timer, bootstrap module, and charge pump to generate turn-on voltages for upper and lower driving MOSFETs, enabling dynamic hybrid driving to ensure reliable signal transmission and prevent leakage, with a focus on reducing I/O circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate tracking circuit and floating N-well circuit are used to achieve strong I/O output capability and gate oxide reliability, then the circuit can withstand voltage levels several times the I/O supply voltage, but the chip area and power consumption increase
Solution Approach 1:
The patent changes the voltage parameters dynamically by introducing a voltage regulator circuit that adjusts the voltage level based on operational mode. The circuit switches between different voltage levels (VDD and VDDA) to achieve both high voltage withstanding capability and low power consumption, resolving the contradiction between reliability and chip area
Solution Approach 2:
The patent implements dynamic operation by making the circuit adaptable to different voltage levels and operational modes. The gate tracking circuit and voltage regulator work together to dynamically adjust circuit behavior based on whether the system is in high-voltage or low-voltage mode, achieving both reliability and area efficiency
2Reliability
If PMOS transistors with high threshold are used to solve leakage prevention problems, then leakage is prevented when no power is supplied, but the PMOS transistor in the output stage cannot be turned on when VDD is too low
Solution Approach 1:
The patent introduces an intermediate voltage regulation mechanism that mediates between the high threshold requirement for leakage prevention and the low voltage switching requirement. The voltage regulator circuit acts as an intermediary, providing appropriate gate voltages that enable switching while maintaining leakage prevention through proper threshold management
3Adaptability or versatility
If the I/O circuit is designed to be compatible with multiple communication protocols (I2C and I3C), then the chip can communicate with different types of chips, but the circuit complexity and design difficulty increase
Solution Approach 1:
The patent designs a universal I/O circuit that can operate with multiple communication protocols (I2C and I3C) by implementing a multi-mode voltage regulation system. The circuit uses a single unified structure with configurable voltage levels and timing parameters, allowing it to adapt to different protocols without requiring separate dedicated circuits for each protocol
Solution Approach 2:
The patent achieves protocol compatibility through dynamic configuration of circuit parameters. The voltage regulator and gate tracking circuit can dynamically adjust their operation based on the detected protocol type, enabling the same physical circuit to fulfill multiple protocol requirements without increasing structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively maintains gate oxide reliability and prevents leakage, achieving high-speed signal transmission while minimizing chip area and power consumption, thus addressing the limitations of prior art in multi-protocol compatibility and power management.
Implementation Method 1
a bootstrap module for generating a first turn-on voltage based on the input signal
Implementation Method 2
a charge pump, connected to the timer, for generating a second turn-on voltage based on the timing signal
Data Source
AI summary
A driving output circuit, a chip, and a driving output method are provided; the driving output circuit includes: a timer for outputting a timing signal; a bootstrap module for generating a first turn-on voltage based on an input signal; a charge pump for generating a second turn-on voltage based on the timing signal; a driving module including an upper driving MOSFET and a lower driving MOSFET connected to the upper driving MOSFET, and the upper driving MOSFET is connected to the lower driving MOSFET at a signal output; the first turn-on voltage and the second turn-on voltage are both used to turn on the upper driving MOSFET and/or the lower driving MOSFET to cause the signal output to output an output signal. The present disclosure provides a dynamic hybrid driving output circuit, which has improved gate oxide reliability and an enhanced anti-leakage function when not powered.