Hybrid III-Nitride and Silicon MOSFET Circuit for Transient Voltage Control
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Solution Overview
Problem
Conventional power devices made of silicon have limitations in high-frequency and high-voltage performances due to silicon's limited critical electric field and high resistance, while III-Nitride semiconductors offer better properties but face challenges in achieving desired performances, especially with thermal and transient voltage issues in cascode structures.
Innovation Solution
A hybrid transistor circuit is developed, comprising a Silicon-based MOSFET and a III-Nitride FET connected in series, with a driver unit providing separate switching signals to control the transistors' turn-on and turn-off sequences, minimizing high-voltage and high-current overlap and reducing off-state leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cascode structure with normally-on III-N transistor and normally-off Si MOSFET is used, then normally-off behavior is achieved, but thermal and transient voltage issues occur during high-frequency operations
Solution Approach 1:
The patent divides the control of the III-N transistor into two separate gate terminals: a first gate terminal for controlling the channel formation and a second gate terminal for controlling the current flow. This segmentation allows independent optimization of threshold voltage control and transient voltage protection, resolving the thermal and transient voltage issues while maintaining normally-off behavior.
Solution Approach 2:
The patent introduces an intermediate barrier layer between the channel layer and the second gate electrode. This barrier layer acts as a mediator that controls the interaction between the second gate terminal and the channel, enabling precise control of the current flow while protecting against transient voltage spikes and reducing thermal effects during high-frequency operations.
2Reliability
If enhancement mode operations are used in III-N transistors, then normally-off behavior is achieved, but device performance degrades with low threshold voltages and high off-state leakage currents
Solution Approach 1:
The patent segments the gate control into two independent gate terminals, where the first gate terminal establishes a threshold voltage for channel formation and the second gate terminal controls the current flow. This segmentation enables the transistor to achieve low off-state leakage current while maintaining appropriate threshold voltage levels, resolving the performance degradation issue.
Solution Approach 2:
The patent changes the control parameters by introducing a second gate terminal that independently controls the current flow parameter. This allows dynamic adjustment of the transistor's operating state, enabling low off-state leakage current while maintaining device performance through optimized parameter control.
3Object-affected harmful factors
If separate gate terminals are used to control III-N transistor, then transient voltage issues are reduced, but device complexity increases
Solution Approach 1:
The patent segments the gate control function into two terminals, which increases control capability but requires careful structural integration. The segmented gate structure is implemented within the existing transistor architecture, minimizing the increase in overall device complexity while achieving reduced transient voltage issues.
Solution Approach 2:
The patent designs the dual-gate structure to serve multiple functions: the first gate terminal controls channel formation, the second gate terminal controls current flow and provides transient voltage protection. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.
Data Source
AI summary
A hybrid transistor circuit is disclosed for use in III-Nitride (III-N) semiconductor devices, comprising a Silicon (Si)-based Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Group III-Nitride (III-N)-based Field-Effect Transistor (FET), and a driver unit. A source terminal of the III-N-based FET is connected to a drain terminal of the Si-based MOSFET. The driver unit has at least one input terminal, and two output terminals connected to the gate terminals of the transistors respectively. The hybrid transistor circuit is turned on through the driver unit by switching on the Silicon-based MOSFET first before switching on the III-N-based FET, and is turned off through the driver unit by switching off the III-N-based FET before switching off the Silicon-based MOSFET. Also disclosed are integrated circuit packages and semiconductor structures for forming such hybrid transistor circuits. The resulting hybrid circuit provides power-efficient and robust use of III-Nitride semiconductor devices.