Hybrid MRAM Cache Segregating Single-Ended and Differential Sensing
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Solution Overview
Problem
Implementing a hybrid cache architecture that combines static random access memory (SRAM) and magnetoresistive random access memory (MRAM) is challenging due to differences in bit cell sizes, making it difficult to achieve a balanced tradeoff between access speed and bit cell density.
Innovation Solution
A hybrid cache architecture using solely MRAM-based caches with two types of bit cell sensing: single-ended and differential, resulting in a uniform bit cell array but a non-uniform sense amplifier configuration, allowing for a slower but denser cache region and a faster cache region within the same MRAM bit cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a magnetoresistive random access memory (MRAM)-based cache is used, then bit cell density is improved, but access speed deteriorates
Solution Approach 1:
The patent segments the uniform MRAM bit cell array into multiple regions, each region being associated with a different sense amplifier type (single-ended or differential). This segmentation allows different portions of the array to have different access speeds while maintaining uniform bit cell density throughout, effectively resolving the contradiction between high density and variable speed requirements.
Solution Approach 2:
The patent applies local quality by assigning different sense amplifier characteristics to different regions of the MRAM array. Specifically, differential sense amplifiers are used in regions requiring faster access, while single-ended sense amplifiers are used in regions where density is prioritized over speed. This local differentiation allows the system to optimize both density and speed in their respective regions simultaneously.
2Adaptability or versatility
If a hybrid cache architecture combining SRAM and MRAM is implemented, then a balance between access speed and bit cell density is achieved, but device complexity increases due to different bit cell sizes
Solution Approach 1:
The patent merges the functionalities of separate SRAM and MRAM cache regions into a single unified MRAM-based array. By using the same bit cell design throughout the array and differentiating only the sense amplifier types, the patent eliminates the complexity associated with integrating two different bit cell technologies while still achieving the desired balance between speed and density.
Solution Approach 2:
The patent makes the MRAM bit cell array universal by designing it to serve multiple functions that previously required separate memory technologies. The uniform bit cell array can operate in different speed modes depending on which sense amplifier is used, allowing a single structure to fulfill both high-speed and high-density cache requirements without the complexity of heterogeneous integration.
3Speed
If different sense amplifier types are used in different regions of the MRAM bit cell array, then access speed is improved in specific regions, but sense amplifier configuration complexity increases
Solution Approach 1:
The patent segments the sense amplifier configuration to match the segmentation of the bit cell array regions. Each region is independently configured with appropriate sense amplifier types, allowing for localized optimization of access speed without requiring complete redesign of the entire sense amplifier system. This modular approach manages complexity by breaking down the sense amplifier configuration into manageable regional units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a balanced hybrid cache architecture that leverages the high density of MRAM while maintaining performance by segregating bit cells into slower and faster regions based on sensing schemes, optimizing cache efficiency.
Implementation Method 1
A read current may be applied across the magnetic tunnel junction and a resulting current may be sensed to determine a resistance state of the magnetic tunnel junction
Implementation Method 2
The magnetoresistive random-access memory bit cell array may be a spin torque transfer magnetoresistive random-access memory bit cell array
Data Source
AI summary
A hybrid cache architecture uses magnetoresistive random-access memory (MRAM) caches but has two different types of bit cell sensing. One type of bit cell sensing is single-ended and the other type of bit cell sensing is differential. The result is a uniform bit cell array but a non-uniform sense amplifier configuration.