Hybrid-Precision MS Decoder for Long-Code Gate Count Reduction
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Solution Overview
Problem
Min-sum (MS) decoders require a larger gate-count compared to bit-flip (BF) decoders, leading to lower throughput per gate or power consumption, especially when supporting long codes like 8 KB or 16 KB, which exacerbates the issue in system-on-chip (SoC) implementations.
Innovation Solution
A hybrid precision MS decoder is introduced, which determines an operation mode to calculate and store variable-to-check node (V2C) messages, using full information in high precision mode for 4 KB support and partial information in low precision mode for 8 KB/16 KB support, thereby reducing the gate-count and optimizing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full information is stored in CNU memory for high precision mode, then decoding accuracy is improved, but gate-count increases
Solution Approach 1:
The decoder dynamically switches between high precision mode (storing full information including min1, min2, and their indices) and low precision mode (storing only min1 and its index) based on the code length being decoded. This dynamic adaptation allows the system to use full information for short codes where accuracy is critical while using reduced information for long codes where gate-count reduction is prioritized.
Solution Approach 2:
The invention changes the precision parameter of the stored information in CNU memory based on operating conditions. For long codes (8KB, 16KB), it stores partial information with lower precision to reduce gate-count, while for short codes (4KB), it stores full information with higher precision to maintain decoding accuracy. This parameter adaptation resolves the contradiction between accuracy and complexity.
2Productivity
If high precision mode is used for long codes, then decoding performance is improved, but power consumption increases
Solution Approach 1:
The invention adapts the precision parameter of CNU memory storage based on code length. For long codes where decoding performance is already challenging, it uses low precision mode to reduce power consumption while maintaining acceptable performance. For short codes, it uses high precision mode to optimize performance without excessive power penalty.
Solution Approach 2:
The system dynamically adjusts its operating mode based on the decoding task requirements, switching between high precision and low precision modes. This dynamic adjustment allows the decoder to optimize the trade-off between performance and power consumption for different code lengths rather than being locked into a single operating mode.
3Measurement precision
If full check information is stored for all code lengths, then decoding accuracy is maintained, but device area increases
Solution Approach 1:
The invention applies different storage precision requirements to different code length scenarios. For long codes (8KB, 16KB), it stores only essential information (min1 and its index) with reduced precision, while for short codes (4KB), it stores complete information (min1, min2, and indices) with full precision. This local adaptation of quality requirements optimizes the balance between accuracy and area.
Solution Approach 2:
The invention changes the storage parameter (information completeness) in CNU memory based on the code length being processed. By adapting the precision parameter to the specific application scenario, it reduces the memory area required for long codes while maintaining sufficient decoding accuracy.
4Device complexity
If low precision mode is used for long codes, then gate-count is reduced, but decoding reliability may decrease
Solution Approach 1:
The decoder implements dynamic mode switching based on code length characteristics. For long codes where gate-count reduction is most beneficial, it uses low precision mode. For short codes where the system can afford higher complexity, it uses high precision mode to ensure maximum reliability. This dynamic approach optimizes the reliability-complexity trade-off.
Solution Approach 2:
The invention adapts the precision parameter based on the specific decoding task. For long codes, it uses reduced precision to achieve gate-count reduction while accepting a controlled trade-off in reliability. For short codes, it maintains full precision to ensure high reliability when the system capacity allows.
Data Source
AI summary
A method for operating an MS decoder and an associated memory system utilizing the MS decoder. The method determines an operation mode of the MS decoder. For each variable node, the method calculates a variable to check node V2C message. The method stores, in a check node unit CNU memory, check information associated with the calculated V2C message according to the operation mode. The check information includes full information when the operation mode is a high precision mode, and partial information when the operation mode is a low precision mode.