Hybrid Multiplication Unit for FPGA Bitstream Authentication

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Solution Overview

Problem

Conventional reconfigurable circuit devices, such as FPGAs, face significant challenges in implementing bitstream authentication due to the high hardware area requirements of existing ECDSA technologies, which are impractical for resource-constrained devices and vulnerable to attacks, especially with the advent of quantum computing.

Innovation Solution

A lightweight digital signature verification engine is developed using a hybrid design that combines dedicated and configurable elements to optimize large multiplication operations, reducing Logic Element (LE) utilization by employing a 384-bit×9-bit combinatorial multiplier and leveraging embedded memory for intermediate results, resulting in a significantly reduced LE requirement and improved performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ECDSA technology is implemented in reconfigurable circuit devices, then digital signature verification capability is achieved, but hardware area requirements become excessively high (86k logic elements)

Engineering Contradiction:

Improvebitstream authentication capabilityVSAvoidlogic element utilization

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent segments the ECDSA verification engine into multiple functional blocks including Galois Field multiplication unit, elliptic curve point multiplication unit, hash computation unit, and signature verification unit. This segmentation allows each block to be optimized independently for area efficiency while maintaining overall functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from software-based ECDSA implementation to hardware-based implementation using field-programmable gate array (FPGA) devices. This dimensional change from software to hardware enables parallel computation and significantly reduces the operational overhead, making ECDSA verification practical for resource-constrained environments.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If resource-constrained reconfigurable devices are used, then deployment flexibility is improved, but implementation of bitstream authentication becomes impractical due to area constraints

Engineering Contradiction:

Improvedeployment flexibilityVSAvoidavailable logic elements

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by optimizing specific critical path components such as the Galois Field multiplication unit and elliptic curve point multiplication unit with area-efficient architectures. These localized optimizations reduce the overall area requirement while maintaining the security and functionality of the ECDSA implementation.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements a dynamic configuration approach where the ECDSA verification engine can be selectively enabled or disabled based on operational requirements. The engine can also be configured to handle different curve types and key sizes, providing adaptability to various security requirements while optimizing resource usage.

Inventive Principle:

Principle #15Dynamics

3Area of stationary object

If lightweight ECDSA engine is implemented, then logic element requirements are reduced, but verification latency must remain acceptable

Engineering Contradiction:

Improvelogic element utilizationVSAvoidverification latency

Core Design Contradiction:

Area of stationary objectVSLoss of time

Solution Approach 1:

The patent pre-computes and stores lookup tables for common elliptic curve operations and Galois Field arithmetic. These pre-computed values are stored in on-chip memory, allowing the verification engine to quickly retrieve intermediate results without performing full computations in real-time, thereby reducing verification latency.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements a pipelined architecture where multiple verification operations can proceed in parallel through different stages of the computation pipeline. This continuous processing ensures that verification latency is minimized while maintaining high throughput, allowing the lightweight engine to meet real-time security requirements.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS12047514B2Digital signature verification engine for reconfigurable circuit devices

Publication Date: 2024.07.23 ALTERA CORP

AI summary

Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.