Hybrid Multiplier-Adder Circuit for Precision and Power Balance
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Solution Overview
Problem
Multiplier-adders face challenges in achieving a balance between power consumption and precision when implementing addition using digital or analog circuits.
Innovation Solution
A circuit design that combines digital and analog addition circuits, where digital accumulation is performed on higher-position bits for precision and analog accumulation on lower-position bits to reduce power consumption, with an optional analog-to-digital converter to combine results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital addition circuit is used to perform accumulation, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent segments the accumulation operation into two distinct circuits: a digital addition circuit for high-position bits (requiring precision) and an analog addition circuit for low-position bits (requiring low power consumption). This segmentation allows each circuit to be optimized for its specific function, resolving the contradiction between precision and power consumption.
Solution Approach 2:
The patent applies local quality by assigning different accumulation methods to different bit positions based on their specific requirements. High-position bits use digital accumulation for precision, while low-position bits use analog accumulation for energy efficiency. This localized optimization resolves the global contradiction by addressing the specific needs of different parts of the system.
2Use of energy by moving object
If analog addition circuit is used to perform accumulation, then use of energy is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent segments the accumulation operation into two distinct circuits: a digital addition circuit for high-position bits (requiring precision) and an analog addition circuit for low-position bits (requiring low power consumption). This segmentation allows each circuit to be optimized for its specific function, resolving the contradiction between precision and power consumption.
Solution Approach 2:
The patent applies local quality by assigning different accumulation methods to different bit positions based on their specific requirements. High-position bits use digital accumulation for precision, while low-position bits use analog accumulation for energy efficiency. This localized optimization resolves the global contradiction by addressing the specific needs of different parts of the system.
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AI summary
A circuit, a multiplier-adder, and a circuit optimization method are provided, and relate to the field of electronic devices, to achieve a balance between power consumption and precision of the multiplier-adder. The circuit includes a digital addition circuit and an analog addition circuit. The digital addition circuit is configured to perform bitwise digital accumulation on bits that belong to a first bit position range and that are in a plurality of groups of partial products. The plurality of groups of partial products are obtained by multiplying a plurality of first values by a plurality of second values. The first bit position range refers to S bit positions of a product value of one of the first values and one of the second values. S is a positive integer. The product value is obtained by performing bitwise accumulation after a group of partial products are shifted. The analog addition circuit is configured to perform bitwise analog accumulation on analog parameters corresponding to values of bits that belong to a second bit position range and that are in the plurality of groups of partial products. The second bit position range refers to T bit positions that are of the product value and that do not overlap the first bit position range. T is a positive integer. S + T is less than or equal to a quantity of bit positions of the product value.