Hybrid Multithreading Framework for Irregular Memory Access

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Solution Overview

Problem

Traditional microprocessor designs struggle with efficient scheduling of concurrent applications in multithreaded processors, particularly when dealing with irregular or non-unit stride memory access patterns, leading to suboptimal performance and power utilization due to long latency events and inadequate control over thread concurrency.

Innovation Solution

A hybrid multithreading framework (HMTF) with a modular processor architecture and instruction set that allows for dynamic power gating and explicit control over context switching, enabling efficient execution of highly concurrent applications with irregular memory access patterns by participating in hardware scheduling and utilizing extended memory semantics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If traditional microprocessor designs are used with function pipe perspective, then core arithmetic unit performance is optimized, but processing time is lost during long latency events due to stalling

Engineering Contradiction:

Improvecore arithmetic unit performanceVSAvoidprocessing time during long latency events

Core Design Contradiction:

PowerVSLoss of time

Solution Approach 1:

The patent implements a branch predictor that performs preliminary action by predicting branch outcomes before they are actually resolved. The branch predictor analyzes historical branch behavior and predicts whether a branch will be taken or not taken, allowing the processor to speculatively execute along the predicted path. This preliminary prediction action prevents stalling by preparing execution paths in advance, thus reducing the processing time loss during what would otherwise be long latency branch resolution events.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If multithreading is implemented with fixed context switching periods, then concurrent execution is achieved, but control over thread concurrency is inadequate

Engineering Contradiction:

Improveconcurrent executionVSAvoidcontrol over thread concurrency

Core Design Contradiction:

ProductivityVSEase of operation

Solution Approach 1:

The patent implements dynamic context switching control where the processor can adjust thread switching behavior based on runtime conditions. The control logic monitors thread execution states, memory access patterns, and performance metrics to dynamically determine when context switching should occur. This dynamic approach replaces fixed periodic switching with adaptive switching that responds to actual system conditions, providing both concurrent execution capability and fine-grained control over thread concurrency behavior.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent incorporates feedback mechanisms where performance monitoring units track thread execution efficiency, memory access latency, and resource utilization. This feedback information is used by the context switching controller to adjust scheduling decisions in real-time. The feedback loop enables the system to learn from past performance and optimize thread concurrency control dynamically, achieving both high productivity through concurrent execution and ease of operation through adaptive control.

Inventive Principle:

Principle #23Feedback

3Speed

If data cache locality is optimized for regular access patterns, then cache performance is improved, but performance deteriorates for irregular or non-unit stride memory access patterns

Engineering Contradiction:

Improvecache access speedVSAvoidhandling of irregular memory access patterns

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements a cache replacement policy that dynamically changes cache parameters based on access patterns. The system monitors memory access characteristics including stride patterns, access frequency, and temporal locality. When irregular or non-unit stride patterns are detected, the cache controller adjusts replacement policies and associativity parameters to better accommodate these patterns. This parameter adaptation allows the cache to maintain high performance for both regular and irregular access patterns by changing its behavior to match the actual workload characteristics.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10430190B2Systems and methods for selectively controlling multithreaded execution of executable code segments

Publication Date: 2019.10.01 MICRON TECHNOLOGY INC

AI summary

Systems and methods which provide a modular processor framework and instruction set architecture designed to efficiently execute applications whose memory access patterns are irregular or non-unit stride are disclosed. A hybrid multithreading framework (HMTF) of embodiments provides a framework for constructing tightly coupled, chip-multithreading (CMT) processors that contain specific features well-suited to hiding latency to main memory and executing highly concurrent applications. The HMTF of embodiments includes an instruction set designed specifically to exploit the high degree of parallelism and concurrency control mechanisms present in the HMTF hardware modules. The instruction format implemented by a HMTF of embodiments is designed to give the architecture, the runtime libraries, and/or the application ultimate control over how and when concurrency between thread cache units is initiated. For example, one or more bit of the instruction payload may be designated as a context switch bit (CTX) for expressly controlling context switching.