Hybrid NAND Memory Array Using Ferroelectric Cache Blocks
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Solution Overview
Problem
Charge trap memory cells exhibit slower read and write speeds compared to ferroelectric memory cells due to higher bias voltages, limiting the performance of NAND memory devices.
Innovation Solution
Integration of ferroelectric memory cell blocks with charge trap memory cell blocks in NAND memory devices to create a hybrid memory array, utilizing ferroelectric memory cells as a high-performance cache to enhance overall speed and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge trap memory cells are used in NAND memory devices, then non-volatile storage capacity is achieved, but read and write speeds become slower
Solution Approach 1:
The memory device is segmented into two distinct memory arrays: a first memory array using charge trap memory cells for non-volatile storage, and a second memory array using ferroelectric memory cells for high-speed operations. This segmentation allows each type to operate in its optimal performance regime without compromising the other.
Solution Approach 2:
The control logic acts as an intermediary that automatically manages data flow between the two memory arrays. It determines when to use the charge trap array for storage and when to use the ferroelectric array for high-speed access, effectively mediating between the conflicting requirements of non-volatility and speed.
2Ease of manufacture
If charge trap memory cells operate at higher bias voltages, then programming capability is achieved, but power consumption increases
Solution Approach 1:
The memory system is divided into two arrays with different voltage characteristics. The ferroelectric memory array operates at lower bias voltages, reducing overall power consumption while maintaining programming capability through the combined architecture of both arrays.
Solution Approach 2:
The system changes the operating voltage parameter by using ferroelectric memory cells that can be programmed at lower voltages compared to charge trap memory cells. This parameter change directly addresses the power consumption issue while preserving programming functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid memory array achieves improved read and write speeds, closing the performance-cost gap between NAND memory and DRAM by providing a high-performance cache with a NAND cost structure.
Implementation Method 1
ferroelectric memory cells, which may include a ferroelectric layer in place of the charge trap layer
Implementation Method 2
Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps)
Data Source
AI summary
A memory device include an array of memory cells and control logic. The array of memory cells includes charge trap memory cells and ferroelectric memory cells. The control logic is configured to access the array of memory cells. The array of memory cells may include a first string of series-connected charge trap memory cells where each charge trap memory cell includes a first gate stack structure. The array of memory cells may include a second string of series-connected ferroelectric memory cells where each ferroelectric memory cell includes a second gate stack structure different from the first gate stack structure.