Hybrid Neuromorphic Analog-Digital Processor for Low Power Edge Inference
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Solution Overview
Problem
Conventional hardware implementations for neural networks face challenges in keeping pace with the growing complexity of neural networks, particularly in terms of power consumption and reconfigurability, as digital microprocessors plateau and neuromorphic processors are limited in applications due to high power and speed constraints, with no known solutions providing low enough power consumption for edge environments.
Innovation Solution
The development of hybrid neuromorphic analog signal processors that combine a fixed portion for pattern detection with a flexible portion for classification or regression, utilizing arrays of memristors and SuperFlash memory, allowing for reconfiguration and low power consumption, enabling efficient edge computing and IoT applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional digital microprocessors are used for neural network computations, then computational power can be maintained, but power consumption increases and performance plateaus
Solution Approach 1:
The patent replaces conventional digital microprocessor architectures with neuromorphic processors that emulate biological neural networks. This substitution uses event-driven spike-based communication instead of traditional von Neumann architecture, dramatically reducing data transmission power consumption while maintaining computational capabilities for neural network operations
Solution Approach 2:
The patent changes the fundamental operating parameters of the computing system by adopting sparse, event-driven spike trains instead of continuous data streams. This parameter change reduces the volume of data transmission by orders of magnitude, directly addressing the power consumption issue while maintaining computational throughput
2Use of energy by moving object
If neuromorphic processors are used for low power consumption, then power efficiency improves, but speed and application versatility are limited
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling in the neuromorphic processor, allowing the system to adapt its operating speed to the computational demands of different applications. This dynamic adjustment enables the processor to operate at higher speeds when needed while maintaining low power consumption during normal operation
Solution Approach 2:
The patent uses periodic clock cycles and batch processing mechanisms that allow the neuromorphic processor to accumulate computational work and process it in periodic intervals. This approach enables higher throughput for time-critical applications while maintaining average power consumption at low levels
3Ease of manufacture
If fixed weight neuromorphic processors are manufactured, then manufacturing cost is reduced, but reconfigurability for new applications is lost
Solution Approach 1:
The patent segments the neuromorphic processor into fixed-weight core units and a separate programmable weight memory subsystem. This segmentation allows the majority of the processor to be manufactured with fixed, optimized connectivity patterns at low cost, while the programmable memory enables software-based reconfiguration of weights for different applications
Solution Approach 2:
The patent introduces a programmable weight memory as an intermediary between the fixed neuromorphic compute units and the input data. This intermediary layer allows the system to load different weight sets from memory for different applications, providing reconfigurability without requiring changes to the physical processor architecture
Data Source
AI summary
A hybrid analog-digital hardware apparatus and a method for realizing the hardware apparatus are provided. The hardware apparatus includes an analog circuit that includes a plurality of operational amplifiers and a plurality of resistors. The analog circuit is configured to receive an analog signal from one or more sensors, and compute an analog output based on the analog signal, by performing a portion of a trained neural network. In some implementations, the hardware apparatus includes an analog-to-digital converter coupled to the analog circuit and configured to receive and convert the analog output to a digital input. The hardware apparatus also includes a classifier or regression circuit coupled to the analog circuit. The classifier or regression circuit is configured to receive output (e.g., a set of embeddings) from the analog circuit, and classify the output to obtain a result according to a machine learning model.