Hybrid NoC Synchronization Switch for Many-Core Neural Accelerators
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Solution Overview
Problem
Existing neural network accelerators with 2D mesh network-on-chip designs face challenges such as complex parsing logic, complex control signal routing, and congestion on physical links due to combined data and control signal transmissions, which hinder efficient synchronization and communication among cores.
Innovation Solution
A hybrid Network-on-Chip architecture with decoupled data and control signal channels, utilizing a global synchronization switch for dynamic core-to-core connections, allowing instantaneous control signal exchange and maintaining a mesh topology for data transmission, enabling out-of-order computation and reducing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data and control signals share the same physical channels in 2D mesh NoC, then wiring is clean and organized, but parsing logic becomes complex and control signal routing becomes complex
Solution Approach 1:
The patent segments the physical channels into separate data channels and control signal channels. Each core has dedicated data channels for data transmission and dedicated control channels for control signal transmission, eliminating the need for complex parsing logic while maintaining clean wiring layout through modular channel separation.
Solution Approach 2:
The patent introduces a control signal router as an intermediary component that handles control signal routing separately from data routing. This intermediary device simplifies the overall system by dedicatedly managing control signals through separate channels, reducing the complexity burden on individual cores.
2Ease of manufacture
If data and control signals share the same physical channels in 2D mesh NoC, then wiring is clean and organized, but control signal routing mechanism becomes complex
Solution Approach 1:
The patent segments the routing functions by providing dedicated control channels that are separate from data channels. This allows independent routing mechanisms for control signals, simplifying the routing logic while maintaining organized wiring through dedicated pathways.
Solution Approach 2:
The control signal router serves as an intermediary that centralizes control signal routing decisions. By separating control signals from data streams, the router can manage routing complexity centrally rather than distributing it across all cores, simplifying the overall routing mechanism.
3Ease of manufacture
If data and control signals share the same physical channels in 2D mesh NoC, then wiring is clean and organized, but link congestion increases
Solution Approach 1:
The patent segments the shared physical channels into separate data channels and control channels. This segmentation eliminates competition between data and control signals for the same bandwidth, preventing link congestion while maintaining organized wiring through dedicated separate pathways.
Solution Approach 2:
The patent extracts control signals from the data channels and places them in dedicated control channels. By taking out control signals from the shared medium, the system eliminates the congestion problem that arises when both data and control signals compete for the same physical resources.
4Device complexity
If centralized control signal routing is used, then control signal transmission is simplified, but synchronization efficiency decreases due to sequential processing
Solution Approach 1:
The patent implements dynamic control signal routing where the control signal router can simultaneously establish connections between multiple core pairs. Rather than processing control signals sequentially, the system dynamically creates parallel control channels, enabling concurrent synchronization operations and improving efficiency while maintaining routing simplicity.
Solution Approach 2:
The patent transitions from a single-dimensional sequential control signal processing approach to a multi-dimensional parallel approach. By creating multiple simultaneous control channels through the control signal router, the system adds a temporal and spatial dimension to control signal transmission, enabling parallel synchronization without increasing routing complexity.
Data Source
AI summary
This application describes a network-on-chip system that could be used in a hardware accelerator for accelerating neural network computations. An example NoC system may include a plurality of cores, and a plurality of data links connecting adjacent cores of the plurality of cores for transmitting data. The example NoC may further include a global synchronization switch connected to each of the plurality of cores. The global synchronization switch is configured to dynamically connect any pair of cores in the plurality of cores for transmitting control signals between the pair of cores.