Hybrid NoC Wireless Interconnects for On-Chip Congestion

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Solution Overview

Problem

Network-on-chip (NoC) architectures face bottlenecks due to network traffic congestion, limiting further performance improvements in parallel computing systems with multiple interconnected cores, particularly in terms of energy efficiency and communication latency.

Innovation Solution

Implementing a hybrid NoC architecture with both wired and wireless interconnects to facilitate efficient on-chip communications among computing cores, using a hierarchical organization of subnets with wired and wireless interfaces to selectively route messages based on propagation length, thereby optimizing communication pathways and reducing congestion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wired interconnects are used for on-chip communications, then connection reliability is improved, but network traffic congestion increases and energy consumption rises

Engineering Contradiction:
Improveconnection reliabilityVSAvoidcommunication efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines wired and wireless interconnect technologies into a hybrid NoC architecture. Wired interconnects provide reliable short-range communications, while wireless interconnects handle long-range communications, merging the advantages of both technologies to resolve the contradiction between reliability and communication efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the communication network into wired subnets and wireless subnets based on communication distance and traffic patterns. This segmentation allows different communication modes to be used appropriately, reducing overall network congestion and improving productivity while maintaining reliability through the wired portion.

Inventive Principle:
Principle #1Segmentation

2Stability of the object's composition

If wired interconnects are used for on-chip communications, then connection stability is improved, but energy consumption increases

Engineering Contradiction:
Improveconnection stabilityVSAvoidenergy consumption
Core Design Contradiction:
Stability of the object's compositionVSUse of energy by moving object

Solution Approach 1:

The patent applies different interconnect qualities to different spatial locations and communication scenarios. Wired interconnects with high stability are used for short-range, high-reliability communications, while wireless interconnects are used for long-range communications where wired connections would consume excessive energy. This local differentiation resolves the contradiction between stability and energy consumption.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If traditional NoC architectures are used, then manufacturing simplicity is maintained, but scalability is limited

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidscalability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal NoC architecture that can adapt to different scale requirements and application scenarios. The hybrid wired-wireless interconnect system can be configured for various computing system sizes and workloads, providing scalability while maintaining manufacturing feasibility through standardized modular components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9876708B2Network-on-chip computing systems with wireless interconnects
Publication Date: 2018.01.23 WASHINGTON STATE UNIVERSITY
  • US9876708B2 patent drawing
  • US9876708B2 patent drawing
  • US9876708B2 patent drawing

AI summary

Several embodiments of the present technology are related to network-on-chip based integrated circuits with wireless interconnects. In one embodiment, a computing device includes a plurality of computing cores on a common substrate. The computing cores are organized into a plurality of subnets individually associated with a set of the computing cores, a communications hub associated with the set of the computing cores, and a plurality of conductive or semi-conductive connectors connecting the set of the computing cores into a small world network. The computing device further includes a plurality of wireless transceivers on the substrate, the wireless transceivers being individually associated with one of the communications hubs of a corresponding subnet.