Hybrid Node Chiplet Stacking for AI-Guided 3D Package Partitioning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in efficiently integrating advanced IC packaging technologies to enhance density and performance while reducing costs and manufacturing time.
Innovation Solution
A method using artificial intelligence to disassemble single chip designs into chiplets with different functions and process nodes, and integrate them into stacked chip packages, optimizing power, performance, area, and cost (PPAC) specifications through machine learning and high-performance computing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple ICs are vertically stacked in 3D packages to increase density, then functional density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments a single high-density IC chip into multiple lower-density chiplets that can be independently manufactured using existing processes. These chiplets are then integrated into a 3D stacked package, achieving high functional density without requiring complex single-chip manufacturing. The segmentation allows each chiplet to be produced with current manufacturing capabilities while the final assembly achieves the desired density through vertical stacking.
2Reliability
If advanced IC packaging technologies are integrated to enhance performance, then system performance is improved, but integration difficulty increases
Solution Approach 1:
The patent introduces an interposer as an intermediary component that facilitates the integration of multiple chiplets in a 3D stacked package. The interposer provides standardized interfaces and connection points, simplifying the integration process. By using this intermediary substrate, the system achieves enhanced performance through advanced packaging while reducing integration difficulty, as the interposer manages the complexity of connecting multiple chiplets with different interfaces and requirements.
3Reliability
If single chip designs are used to meet performance metrics, then performance is achieved, but manufacturing cost increases
Solution Approach 1:
The patent segments a single high-performance chip design into multiple chiplets that can be manufactured using existing, less costly fabrication processes. Each chiplet is designed to meet specific functional requirements while being producible with current manufacturing capabilities. The overall system performance is achieved through the integration of these chiplets in a 3D stacked package, avoiding the need for expensive next-generation single-chip manufacturing while maintaining performance metrics.
4Quantity of substance
If feature size is reduced to increase integration, then functional density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from increasing functional density through lateral feature size reduction to achieving density through vertical stacking of chiplets. Instead of making features smaller on a single chip plane, the solution stacks multiple chiplets vertically, utilizing the third dimension. This approach achieves high functional density without requiring extreme manufacturing precision for feature size control, as each chiplet can be manufactured with standard precision requirements.
Data Source
AI summary
The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.