Hybrid On-Chip Regulator for High Voltage Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional voltage regulators for CMOS technology face challenges in maintaining stable output high voltage levels across different power supplies and process conditions, leading to voltage ripple and instability, especially when dealing with high capacitive loads and varying temperature conditions.
Innovation Solution
A hybrid on-chip regulator is introduced that uses a reference voltage to limit output high voltage, employing a combination of NMOS and PMOS transistors with capacitive stabilization and a comparator to manage the current path, ensuring stable output voltage levels and reducing the need for external capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional voltage regulator is used to limit output high voltage, then the output voltage can be controlled, but voltage ripple increases and power efficiency decreases under high capacitive loads
Solution Approach 1:
The regulator output is segmented into multiple parallel PMOSFET devices instead of using a single regulator, allowing the capacitive load to be distributed across multiple devices. This segmentation reduces the burden on each individual device, improving power efficiency while maintaining voltage stability through the combined effect of multiple parallel paths.
Solution Approach 2:
A native NMOSFET device is introduced as an intermediary between the PMOSFET regulator devices and the capacitive load. This native NMOSFET acts as a buffer that stabilizes the output voltage by providing additional drive capability during transient conditions, thereby reducing voltage ripple and improving overall voltage stability without increasing power consumption of the main PMOSFET regulators.
2Device complexity
If a single PMOSFET device is used as voltage regulator, then the circuit is simple, but the device may be overloaded under high capacitive loads
Solution Approach 1:
The regulator is divided into multiple parallel PMOSFET devices, each handling a portion of the total capacitive load. This segmentation prevents any single device from being overloaded while maintaining relatively simple circuit architecture through the use of parallel identical devices that can be easily replicated and integrated.
Solution Approach 2:
Multiple PMOSFET regulator devices are merged in parallel configuration to share the total load capacity. The native NMOSFET devices are also merged to provide collective stabilization. This merging approach combines the capabilities of multiple devices to handle high capacitive loads reliably while keeping individual device complexity low.
3Adaptability or versatility
If output high voltage is limited to match logic high voltage levels, then compatibility between chips is improved, but the ability to utilize higher power supply voltages is restricted
Solution Approach 1:
The native NMOSFET devices serve as intermediary elements between the high voltage power supply and the logic level output. These intermediaries enable the system to accept higher power supply voltages for improved power efficiency while automatically limiting the output high voltage to the required logic level through the inherent characteristics of the native NMOSFET, thus maintaining chip compatibility without restricting power supply voltage utilization.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A driver circuit (300) provides fast settling times, slew rate control, and power efficiency, while reducing the need for large external capacitors (340). A voltage reference circuit (310) generates a voltage reference signal (Vref ). A comparator (330) compares the voltage reference signal and a driver output signal (320) and generates an output high voltage control signal. An output driver (320) includes a first (321) and a second (322) switch that are coupled together. The first and second switches are further coupled to generate the driver output signal in response to coupling the output high voltage control signal (333) to the control terminal of the first switch and coupling an input signal (power down) to the control terminal of the second switch.