Hybrid Orientation SOI Substrates for CMOS Performance
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Solution Overview
Problem
Current semiconductor technology limits the performance of CMOS devices by using single crystal plane substrates, which are either optimal for n-channel or p-channel field effect transistors but not both, due to differences in electron and hole mobility, leading to suboptimal performance for hybrid orientation substrates where one region is bulk-like and the other is SOI.
Innovation Solution
A hybrid orientation substrate is created with one region having a buried insulator layer for a SOI configuration and another region with a counter-doped semiconductor layer for a pseudo-SOI configuration, both with different surface crystallographic orientations, to optimize the performance of both n-FETs and p-FETs by isolating semiconductor device layers from the base substrate and creating floating bodies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single crystal plane substrate is used, then the performance of one type of FET is optimized, but the performance of the complementary FET type deteriorates
Solution Approach 1:
The substrate is divided into multiple device regions, each with different surface orientations. Specifically, first device regions have a first surface orientation optimized for n-FETs, while second device regions have a second surface orientation optimized for p-FETs. This segmentation allows each FET type to operate on its optimal crystal plane, resolving the contradiction between optimizing one FET type while maintaining compatibility with both types.
Solution Approach 2:
Different regions of the substrate are assigned different local properties (surface orientations) to match the specific requirements of each FET type. The first device regions possess the crystallographic orientation that maximizes electron mobility for n-FETs, while the second device regions possess the orientation that maximizes hole mobility for p-FETs. This local differentiation enables each region to independently optimize for its specific device type.
2Ease of manufacture
If hybrid orientation substrate is used with one bulk-like region and one SOI region, then manufacturing complexity is reduced, but device performance deteriorates
Solution Approach 1:
The substrate is segmented into multiple SOI regions, each with different surface orientations, rather than having only one SOI region and one bulk-like region. First device regions form first SOI structures with a first surface orientation, while second device regions form second SOI structures with a second surface orientation. This segmentation ensures that all device regions benefit from SOI advantages while maintaining orientation-specific optimization.
Solution Approach 2:
Each device region is assigned the appropriate local property (surface orientation) based on its specific FET type requirements. The first SOI structures have the crystallographic orientation optimized for n-FETs, while the second SOI structures have the orientation optimized for p-FETs. This local quality differentiation allows both regions to achieve full SOI performance benefits rather than mixing SOI and bulk configurations.
Data Source
AI summary
The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.