Hybrid Output Driver Data Paths for High and Low Voltage Signaling

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Solution Overview

Problem

Existing output drivers face inefficiencies in accommodating both high-voltage and low-voltage signaling standards, leading to excessive capacitive loading that hinders high-speed signaling, particularly in systems-on-a-chip (SoC) for mobile applications.

Innovation Solution

A hybrid data path for a hybrid output driver is implemented, featuring multiplexers for high-voltage and low-voltage data paths that allow for seamless switching between modes, using thick-oxide and thin-oxide transistors to manage pull-up and pull-down signals across varying power supply voltages, ensuring efficient signaling in both high-voltage and low-voltage modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If both high-voltage and low-voltage output drivers are multiplexed to a single output terminal, then the output driver can accommodate both high-voltage and low-voltage I/O standards, but the output terminal is loaded with excessive output capacitance that hinders high-speed signaling

Engineering Contradiction:
Improveaccommodation of both high-voltage and low-voltage I/O standardsVSAvoidhigh-speed signaling capability
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent divides the single output terminal into two separate output terminals: a first output terminal for high-voltage signaling and a second output terminal for low-voltage signaling. This segmentation eliminates the capacitive loading problem that occurred when both drivers shared a single terminal, as each terminal now has its own dedicated driver without excessive capacitance from multiplexed drivers.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If a single output terminal is used for both high-voltage and low-voltage drivers, then device complexity is reduced, but the output capacitance increases excessively

Engineering Contradiction:
Improvenumber of output terminalsVSAvoidoutput capacitance loading
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the shared output terminal configuration into two separate terminals, each dedicated to a specific voltage domain. This resolves the harmful capacitive loading effect by ensuring that each output terminal is driven by only one output driver, eliminating the accumulation of capacitance from multiple multiplexed drivers.

Inventive Principle:
Principle #1Segmentation

3Speed

If separate output terminals are provided for high-voltage and low-voltage drivers, then high-speed signaling is enabled by reducing output capacitance loading, but device complexity increases

Engineering Contradiction:
Improvehigh-speed signaling capabilityVSAvoidnumber of output terminals and drivers
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The output driver circuit is designed with a unified control structure that can operate in different modes (high-voltage mode, low-voltage mode, or both simultaneously) depending on configuration. This multi-functionality allows the driver to accommodate both I/O standards while maintaining a relatively simple overall architecture, reducing the impact of the increased terminal count on device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP3912046B1High-voltage and low-voltage data paths of a hybrid output driver
Publication Date: 2024.04.24 QUALCOMM INC
  • EP3912046B1 patent drawingFigure 1A
  • EP3912046B1 patent drawingFigure 1B
  • EP3912046B1 patent drawingFigure 1C

AI summary

A hybrid output data path is provided that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.