Hybrid Oxide Gate Driver Circuitry for OLED Displays
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Solution Overview
Problem
Designing gate driver circuitry for OLED displays is challenging due to the need for transistors with different device characteristics, such as high mobility and negative threshold voltage for depletion mode devices and low mobility with positive threshold voltage for enhancement mode devices, which conventional gate drivers with a single type of semiconducting oxide transistors cannot effectively address.
Innovation Solution
Implementing a hybrid gate driver circuitry using a combination of depletion mode and enhancement mode semiconducting oxide transistors with different mobility and threshold voltage characteristics, where depletion mode transistors with high mobility are used in the output buffer sub-circuit and enhancement mode transistors with lower mobility are used in the logic sub-circuit, along with distinct power supply voltages to manage and deactivate the transistors effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional gate drivers with a single type of semiconducting oxide transistors are used, then the device structure is simple, but the drive current is insufficient and leakage current is high
Solution Approach 1:
The gate driver circuit is segmented into two distinct sub-circuits: an output buffer sub-circuit using depletion mode transistors for high drive current, and a logic sub-circuit using enhancement mode transistors for low leakage current. This segmentation allows each sub-circuit to be optimized for its specific function, resolving the contradiction between drive current capability and device simplicity.
Solution Approach 2:
Different regions of the gate driver circuit are assigned different transistor types based on local functional requirements. The output buffer region uses depletion mode transistors with high mobility for maximum drive current, while the logic region uses enhancement mode transistors with positive threshold voltage for minimal leakage. This local quality differentiation optimizes overall circuit performance.
2Power
If depletion mode transistors with negative threshold voltage are used, then high mobility and drive current are achieved, but the transistors cannot be properly deactivated
Solution Approach 1:
The circuit is divided so that depletion mode transistors are confined to the output buffer sub-circuit where high drive current is needed, while enhancement mode transistors handle the logic sub-circuit where reliable switching and deactivation are critical. This segmentation ensures each transistor type operates in its optimal regime.
Solution Approach 2:
Enhancement mode transistors act as intermediary switching elements that can reliably deactivate the depletion mode transistors. The enhancement mode transistors with positive threshold voltage provide clean switching control, enabling the depletion mode transistors to function effectively without suffering from their inability to be properly deactivated.
3Object-generated harmful factors
If enhancement mode transistors with positive threshold voltage are used, then low leakage current is achieved, but the mobility is lower
Solution Approach 1:
The circuit implements local quality by assigning enhancement mode transistors specifically to the logic sub-circuit where low leakage current is the primary requirement, while depletion mode transistors with high mobility are assigned to the output buffer sub-circuit where drive current capability is critical. This spatial differentiation of transistor types optimizes both leakage and mobility performance in their respective regions.
Data Source
AI summary
A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.