Hybrid Embedded Package With Vertical Die Interconnects for Low Parasitics
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Solution Overview
Problem
Existing semiconductor package designs suffer from significant parasitic effects in applications requiring high-frequency switching of large currents, which negatively impact device performance.
Innovation Solution
A semiconductor package design featuring a hybrid substrate with embedded and mounted semiconductor dies arranged in overlapping configurations, allowing for direct vertical electrical connections with minimized parasitic effects through aligned conductive terminals and short connection paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor package designs are used, then the package structure is simple and easy to manufacture, but parasitic effects (inductance and capacitance) are significant, degrading performance in high-frequency switching applications
Solution Approach 1:
The patent transitions from planar lateral connections to three-dimensional vertical stacking, where semiconductor dies are arranged in overlapping layers with conductive terminals aligned vertically. This dimensional change enables direct vertical electrical connections through the substrate, dramatically reducing connection path length and parasitic effects while maintaining manufacturing feasibility through established vertical interconnect processes.
Solution Approach 2:
The patent embeds one semiconductor die within the substrate while mounting another die on the substrate surface, creating a nested configuration. The embedded die is surrounded by the substrate material, while the mounted die sits on top, with their conductive terminals vertically aligned. This nesting approach maximizes spatial utilization and minimizes inter-die connection distance.
2Object-affected harmful factors
If direct vertical electrical connections are implemented between semiconductor dies, then parasitic inductance and capacitance are minimized, but the alignment precision and manufacturing complexity increase
Solution Approach 1:
The patent pre-configures the substrate with conductive vias and bonding pads at precise locations before mounting the semiconductor dies. The embedded die is positioned and connected to pre-formed substrate conductors, while the mounted die is aligned with pre-marked registration features on the substrate. This preliminary preparation of connection paths and alignment features significantly reduces the actual assembly precision requirements.
Solution Approach 2:
The substrate serves as an intermediary structure that provides both mechanical support and electrical interconnection. It contains pre-formed conductive vias and bonding pads that act as intermediaries between the embedded and mounted dies, facilitating precise electrical connections without requiring direct die-to-die alignment. The substrate's conductor pattern serves as the mediating element that simplifies the overall alignment process.
Data Source
AI summary
A method of producing a semiconductor package includes providing a substrate formed of electrically insulating material and including a die mounting surface, and a first semiconductor die embedded within the substrate, the first semiconductor die including a first conductive terminal that faces the die mounting surface, providing a second semiconductor die that includes a first conductive terminal, and mounting the second semiconductor die on the die mounting surface such that the first conductive terminal of the second semiconductor die faces and is spaced apart from the die mounting surface, a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together is formed, and the second semiconductor die partially overlaps with the first semiconductor die.