Hybrid Package Metallization for Low-Loss Routing and Die Attach
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Solution Overview
Problem
Next-generation multi-chip packaging requires higher interconnect density and lower signal loss at higher frequencies, which is challenging due to the skin effect and conflicting demands for trace roughness reduction and die attach processes, leading to increased costs.
Innovation Solution
The implementation of hybrid metallization features with different surface roughness levels, using semi-additive processing techniques to create low-roughness routing lines and high-roughness die attach pads, with an optional interface material to enhance adhesion and mitigate delamination risks, allowing for high-frequency signal integrity and cost-effective package fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trace roughness is reduced to minimize signal loss at high frequencies, then signal integrity improves, but die attach processes become more difficult and costly
Solution Approach 1:
The patent applies different surface roughness characteristics to different regions of the metallization layer. Specifically, the routing lines have a first surface roughness optimized for low signal loss at high frequencies, while the die attach pads have a second surface roughness optimized for die attach process compatibility. This local differentiation allows each region to have the surface properties it needs without compromising the other function.
2Productivity
If interconnect trace density is increased to support higher bandwidth applications, then signal transmission capacity improves, but trace roughness control becomes more difficult and costly
Solution Approach 1:
The patent enables high interconnect density routing lines to maintain low surface roughness for signal integrity while allowing die attach pads to have higher surface roughness for manufacturability. This is achieved through selective surface treatment or material deposition processes that differentiate between routing line regions and die attach pad regions, allowing each to be optimized independently despite the increased overall density.
3Device complexity
If conventional metallization processes are used for high-density interconnects, then manufacturing simplicity is maintained, but signal loss increases at high frequencies
Solution Approach 1:
The patent modifies the surface roughness parameter of the metallization layer selectively in different regions. For routing lines, the surface roughness is reduced to minimize skin effect losses at high frequencies (28 GHz and above). This is achieved through controlled deposition processes, chemical-mechanical polishing, or etching treatments that alter the surface topology of the metallization without fundamentally changing the conventional metallization process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher interconnect densities and reduced signal losses, supporting bandwidth-intensive applications while maintaining cost-effectiveness by ensuring strong adhesion and integrity in IC device packages.
Implementation Method 1
At higher frequencies, signal transfer becomes more sensitive to the surface of the interconnect metallization features (e.g., lines or traces), a phenomena known as the 'skin effect.'
Data Source
AI summary
IC die package with hybrid metallization surfaces. Routing metallization features have lower surface roughness for reduced high-frequency signal transmission losses while IC die attach metallization features have higher surface roughness for greater adhesion. Routing and die attach features may be formed within a same package metallization level, for example with a plating process. An insulator material may be formed over the surface of the metallization features, for example with a dry film lamination process. Optionally, an interface material may be deposited upon at least the routing features to enhance adhesion of the insulator material to metallization surfaces of low roughness. An opening in the insulator material may be formed to expose a surface of a die attach feature. The exposed surface may be selectively roughened, and an IC die attached to the roughened surface.