Hybrid Packet Memory Architecture for Network Device Buffering

The patent divides the packet memory system into two separate memory components: internal packet memory and external packet memory. Each memory type is used for specific traffic patterns - internal memory handles bandwidth-sensitive flows while external memory handles capacity-sensitive flows. This segmentation allows the system to optimize for both speed and storage capacity simultaneously by matching memory type to traffic requirements.

The patent applies local quality by assigning different memory types to different packet flows based on their specific requirements. Bursty packet flows with lower bandwidth demands are directed to external packet memory for high-capacity buffering, while larger packet flows requiring high access bandwidth are directed to internal packet memory. This localized optimization ensures each memory type operates in its optimal performance zone.

The patent implements dynamic memory selection where the system adaptively chooses between internal and external packet memory based on real-time traffic pattern analysis. The packet processor classifies incoming packet flows and dynamically routes them to the appropriate memory type, allowing the system to flexibly adjust memory usage based on actual traffic demands rather than statically allocating high-bandwidth memory for all flows.

The patent changes the parameter of memory access bandwidth by selecting different memory types based on packet flow characteristics. For larger packet flows that require high access bandwidth to prevent packet drops, the system selects internal packet memory. For smaller bursty flows where storage capacity is more critical than access speed, external packet memory is selected. This parameter-based selection optimizes both reliability and storage utilization.