Hybrid Packet Processing Apparatus with Parallel Flow Paths

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Solution Overview

Problem

Existing network switch designs lack flexibility, as they are typically implemented with fixed hardware circuits, making them inflexible to adapt to different applications and requiring redesign for varying requirements.

Innovation Solution

A packet processing apparatus with hybrid mode architecture using parallel packet flow paths, where one packet processing unit is fully programmable and another is fixed or semi-configurable, allowing for enhanced flexibility and performance by integrating software-defined networking (SDN) and legacy hardware designs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If fixed hardware circuits are used to implement network switch, then packet processing performance is improved, but flexibility and adaptability deteriorate

Engineering Contradiction:
Improvepacket processing performanceVSAvoidflexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The network switch is divided into multiple parallel packet flow paths, with each path containing dedicated fixed hardware circuits for packet processing. This segmentation allows different paths to handle different packet types or protocols simultaneously, maintaining high processing performance while enabling flexibility through selective path activation based on application requirements

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The network switch implements dynamic packet flow path selection mechanisms that can adaptively route packets through different processing paths based on real-time requirements. This dynamic capability allows the system to optimize for either performance or flexibility depending on the specific application scenario, resolving the contradiction between fixed hardware performance and adaptability

Inventive Principle:
Principle #15Dynamics

2Device complexity

If fixed hardware circuits are used to implement network switch, then device complexity is reduced, but adaptability to different applications deteriorates

Engineering Contradiction:
Improvedevice complexityVSAvoidadaptability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The network switch architecture is segmented into multiple independent packet flow paths, each with its own fixed hardware circuits. This modular segmentation reduces the complexity of individual path designs while collectively providing diverse adaptability through parallel specialized units

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The network switch implements universal packet processing capabilities across multiple parallel paths, where each path can be configured or selected to handle different application requirements. This multi-functionality approach maintains relatively simple individual path designs while achieving overall system adaptability through selective path usage

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP2876849B1Packet processing apparatus using packet processing units located at parallel packet flow paths and with different programmability
Publication Date: 2018.01.31 NEPHOS (HEFEI) CO LTD
  • EP2876849B1 patent drawingFigure 1
  • EP2876849B1 patent drawingFigure 2
  • EP2876849B1 patent drawingFigure 3

AI summary

A packet processing apparatus (100) has an ingress packet processing circuit (102), an egress packet processing circuit (104), and a traffic manager (103). The ingress packet processing circuit (102) processes ingress packets received from ingress ports. The egress packet processing circuit (104) processes egress packets to be forwarded through egress ports. The traffic manager (103) deals with at least packet queuing and scheduling. At least one of the ingress packet processing circuit (102) and the egress packet processing circuit (104) includes a first packet processing unit (112, 122) located at a first packet flow path, and a second packet processing unit (114, 124) located at a second packet flow path. The first packet flow path is parallel with the second packet flow path, and programmability of the first packet processing unit (112, 122) is higher than programmability of the second packet processing unit (114, 124).