Hybrid Reconstituted Panel Packaging for Fine RDL and Low Warpage
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Solution Overview
Problem
The increasing core count in modern processing units leads to a 'memory wall' bottleneck and challenges in package warpage for large form-factor packages, necessitating a larger form factor package that integrates logic and memory dies while overcoming manufacturing limitations.
Innovation Solution
A hybrid reconstituted panel level package with a hybrid package architecture, combining fine redistribution layer features and high RDL layer count, is achieved by integrating multiple fan-out packages into a single panel level package through a reconstitution process, leveraging fan-out wafer and panel level packaging techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If core count of processing units is increased to meet high performance computing demand, then computing performance is improved, but package size becomes increasingly difficult to arrange for efficient production
Solution Approach 1:
The processing unit is divided into multiple semiconductor dies (compute dies and memory dies) that are packaged separately as individual sub-packages, then reconstituted into a larger panel-level package. This segmentation allows each die to be optimized independently while achieving high overall performance.
Solution Approach 2:
Multiple semiconductor sub-packages are nested within a single panel-level package structure. The sub-packages containing individual dies are arranged and integrated into the larger FOPLP, creating a nested hierarchy that achieves high computing performance in a manageable form factor.
2Power
If package form factor is increased to integrate logic and memory dies, then memory bandwidth and capacity needs are addressed, but package warpage challenges increase
Solution Approach 1:
The package is segmented into multiple smaller sub-packages that are reconstituted into a panel-level structure. This segmentation distributes the thermal and mechanical stress across multiple smaller units rather than one large monolithic package, reducing warpage while maintaining high memory bandwidth through close integration.
Solution Approach 2:
Different regions of the panel-level package can have different structural characteristics optimized for their specific functions. Memory dies are placed in local proximity to logic dies where high bandwidth is needed, while other regions can be optimized for structural stability and warpage control.
3Manufacturing precision
If fan-out wafer level packaging is used to achieve fine features, then manufacturing precision is improved, but productivity is reduced due to wafer size limitations
Solution Approach 1:
Multiple FOWLP sub-packages are merged into a single panel-level package. This combining approach allows each sub-package to be manufactured with fine features using FOWLP processes, while the final reconstituted package achieves a larger effective area that improves overall production efficiency and yields.
Solution Approach 2:
The solution transitions from two-dimensional wafer-level packaging to three-dimensional panel-level reconstitution. Multiple wafers are processed in parallel and then vertically integrated into a panel-level structure, adding a dimensional aspect that overcomes wafer size limitations while maintaining fine feature precision.
Data Source
AI summary
A semiconductor device and a method of manufacturing the semiconductor device are provided. The method may include forming semiconductor sub-packages by performing a fan-out wafer level packaging process; singulating the semiconductor sub-packages from at least one wafer; and reconstituting the semiconductor sub-packages into a fan-out panel level package (FOPLP).