Hybrid PCM-Flash Memory Segmentation for Execute-in-Place Latency

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Solution Overview

Problem

FLASH memory devices experience significant delays in data access, which limits their application in execute-in-place (XiP) scenarios where programs stored on the memory need to access data multiple times, leading to unacceptable performance.

Innovation Solution

The integration of phase change memory (PCM) with FLASH memory, where data block portions are split between the two types of memory, with PCM handling lower-latency operations and FLASH handling higher-latency operations, allowing for efficient data retrieval and storage by optimizing the size of data block portions based on latency differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If FLASH memory is used for storing data, then cost and portability are improved, but data access latency increases

Engineering Contradiction:

Improvestorage capacityVSAvoiddata access latency

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent divides data into two segments: frequently accessed data is stored in a buffer memory (fast access), while less frequently accessed data is stored in FLASH memory (large capacity). This segmentation resolves the contradiction by providing both fast access for critical data and large capacity for overall storage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different parts of the memory system have different access characteristics. The buffer memory provides low-latency access for hot data, while FLASH memory provides high-capacity storage for cold data. This local quality differentiation allows the system to optimize for both speed and capacity in different locations.

Inventive Principle:

Principle #3Local quality

2Productivity

If data block size is increased for FLASH memory, then storage efficiency is improved, but access latency increases

Engineering Contradiction:

Improvestorage efficiencyVSAvoidaccess latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent segments data access patterns by maintaining a buffer for frequently accessed data blocks and a separate FLASH memory for less frequently accessed data. This allows small, frequently accessed blocks to be quickly retrieved from the buffer while larger, less frequently accessed blocks are stored efficiently in FLASH memory.

Inventive Principle:

Principle #1Segmentation

3Speed

If execute-in-place programming is implemented, then memory bandwidth is improved, but accumulated latency increases

Engineering Contradiction:

Improvememory bandwidthVSAvoidaccumulated latency

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent pre-loads frequently accessed data into the buffer memory before it is needed during execute-in-place operations. This preliminary action ensures that when data is accessed during program execution, it can be retrieved quickly from the buffer rather than experiencing the full latency of FLASH memory access.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10452541B2Nonvolatile storage using low latency and high latency memory

Publication Date: 2019.10.22 MICRON TECHNOLOGY INC

AI summary

Nonvolatile storage includes first and second memory types with different read latencies. FLASH memory and phase change memory are examples. A first portion of a data block is stored in the phase change memory and a second portion of the data block is stored in the FLASH memory. The first portion of the data block is accessed prior to the second portion of the data block during a read operation.